Analog content-addressable memories with memristors

A content-addressable memory compares an input search word against all rows of stored words in an array in a highly parallel manner. While supplying a very powerful functionality for many applications in pattern matching and search, it suffers from large area, cost and power consumption, limiting its use. Past improvements have been realized by using memristors to replace the static random-access memory cell in conventional designs, but employ similar schemes based only on binary or ternary states for storage and search. We propose a new analog content-addressable memory concept and circuit to overcome these limitations by utilizing the analog conductance tunability of memristors. Our analog content-addressable memory stores data within the programmable conductance and can take as input either analog or digital search values. Experimental demonstrations, scaled simulations and analysis show that our analog content-addressable memory can reduce area and power consumption, which enables the acceleration of existing applications, but also new computing application areas.


Introduction
To increase power efficiency and cost performance, there is growing interest in computing architectures that allow for in-memory processing 1 in order to reduce data movement and address the memory wall.In this vein, recent work has shown the promise of using non-volatile memory devices, or memristors, for accelerating matrix multiplication directly in memory arrays, accelerating a range of applications such as machine learning [2][3][4][5][6] , analog signal processing 7,8 , and scientific computing [9][10][11] .The performance improvements from this approach originate from two principles.
First, computation is performed where the data is stored, removing the expensive power and latency costs of data movement between separate computing and memory units in a von-Neumann machine.Second, computation is performed in the analog domain, which provides exponential efficiency gains over digital, particularly at lower precision requirements.Each device performs analog computations that would otherwise require multiple digital elements.Despite the great promise of this approach, demonstrations have thus far been limited to the acceleration of matrix multiplication via crossbars.
Meanwhile, in-memory computational approaches in the digital domain have been extensively explored over the years 12 .While many proposed circuit topologies have not been implemented in commercial systems, content addressable memory (CAM) and the related ternary CAM (TCAM) have stood as a notable exception 13,14 .CAM/TCAM circuits natively perform a matching operation between an input data word (search key) and a stored set of data patterns in the CAM/TCAM array.The operation is highly parallel and another example of an in-memory operation, leading to extremely high throughput compares at low latency, and therefore commercial success in applications such as network routing 15,16 , real-time network traffic monitoring 17 , and access control lists (ACL) 18 .While powerful, CAM performance benefits come at the cost of large power and low memory density, limiting modern usage to high cost niche areas that demand high performance.Recent work has shown that utilizing non-volatile memristors (or resistive memory devices) in TCAM circuits reduces area and power [19][20][21][22][23][24][25][26][27] and provides the flexibility to accelerate powerful finite state machines, particularly for Regular Expression matching used in Network Intrusion Detection Systems 23,28 .However, nearly all memristor-based CAM designs utilize schemes similar to conventional static random-access-memory (SRAM) designs where the memristor only encodes binary states.The highly tunable analog conductance in memristor devices, with many stable intermediate states is not leveraged 29 .
Here, we propose a memristor-based analog CAM that significantly increases data density and reduces operational energy and area for these in-memory processing circuits.Our analog CAM design stores a range of values in each cell using the tunable conductance of memristive devices, and compares an analog input with this stored range to determine a match or mis-match.The concept has been validated with proof-of-concept experiments, as well as simulations to establish performance and scalability.When used to store narrow ranges as discrete levels, our analog CAM can be a direct replacement to digital CAMs, but providing higher memory densities and smaller power consumption.This may enable the use of CAMs for more generic scenarios [30][31][32][33] that otherwise struggle with the limited memory densities and high power consumption of conventional CAMs.More importantly, our analog CAM can store wide intervals of continuous levels, thereby enabling novel search and matching functionality in the analog domain.The analog CAM cell presented here can also be searched with analog input signals, allowing the processing of analog sensor data without the need for an analog-to-digital conversion step.

Results
Six-transistors two-memristors analog content addressable memory The proposed analog CAM concept is illustrated in FIGURE 1, where analog voltage values are input to the analog CAM to be searched against the analog ranges encoded by multilevel conductances in the memristors.This is distinct from all previously reported CAMs (SRAM or memristor-based), where only digital signals are searched and stored (FIGURE 1a).Similar to a digital CAM, the 'match' signal for each row is generated on the matchline (ML) only when all the inputs match the data stored in that row's memory.In contrast to digital CAMs, each analog CAM cell can match a range of analog input voltages (FIGURE 1b), instead of a digital value.The analog CAM can be configured to match a narrow range of discrete values, and therefore one analog CAM cell is a direct functional replacement for multiple digital CAM cells.In addition, similar to storing a 'wild card' or 'X' in the TCAM, the proposed analog CAM also stores a range of continuous values, which would otherwise be difficult to implement with digital CAMs/TCAMs, but (as described later) is beneficial in internet packet (IP) routing, and more novel applications in genomic sequencing, associative memories, decision trees, and random forests.
To realize the proposed analog CAM concept, we have designed an analog CAM cell circuit where each cell is composed of six transistors and two memristors (6T2M) (FIGURE 2a).The analog input search data is mapped to voltage amplitudes V DL applied along datalines (DL), and (CAM) compares the input word against all stored words or rows in parallel.Ternary CAM (TCAM) is an extension where in addition to search/stored '0' and '1' values, 'X' is a wildcard that always yields a match.Data is searched along vertical datalines (DL) and the binary match result of the compare operation between searched and stored words in each row is sensed on horizontal matchlines (ML).The CAM returns the match location of stored data and the searched input (first row here).b, The analog CAM searches and stores analog data, where the input data can be a continuous value, and the stored data is a continuous interval with a lower and upper bound representing an acceptance range for a match.
the stored analog range is configured by the programmed conductances of the two memristors of the cell (FIGURE 2b).Similar to existing CAM circuit implementations, the search operation starts by pre-charging each row's ML to a high logic level, and the MLs stay high (match) only when all of the attached CAM cells of a row match the corresponding input, otherwise discharging and leading to a low logic level (mis-match) on the ML.In the 6T2M design, the ML is connected to pull-down transistors (T1, T2), and is kept high for a 'match' result when the gate voltage of the pull-down transistors is smaller than the threshold voltage, keeping the transistor channel in a high resistance state.
Each analog CAM cell has an upper and lower bound for matching against the input search value.These bounds are encoded by a voltage divider sub-circuit which determines the gate voltage of the pull-down transistor connected to the ML.As shown in FIGURE 2c, the voltage divider subcircuit consists of a transistor and a series connected memristor, which generates the gate voltage (G1) of the pull-down transistor (T1) in the 6T2M analog CAM circuit to embody analog CAM cell's lower match threshold.When V DL is larger than a certain threshold voltage, the transistor is highly conductive and thus the search voltage between SL hi and SL lo (typically at GND) will mainly drop across the M1 memristor, resulting in a small voltage on G1 that does not turn on the pull-down transistor, yielding a match result.The lower bound of the input voltage V DL that yields a match is configured by tuning the memristor conductance in the voltage divider.The upper bound of the search range is configured similarly with an independent voltage divider using M2 and an inverter to control the gate voltage (G2) of the second pull-down transistor (T2) (FIGURE 2b).This concept is shown by the simulation of the voltage on G1 and G2 depending on V DL with of six-transistors and two-memristors (6T2M).The input is represented by the voltage amplitude on the dataline (DL), and the matching result is sensed as the voltage level on the matchline (ML).b, The analog cell will return a 'match' result when the analog input value is within the range (narrow green band) that is stored by the cell.The range is defined by the conductances of two memristors (M1 and M2) in the cell, with M1 determining the lower bound and M2 determining the upper bound of the matching range.c, d, The voltage divider sub-circuits relate the input voltage (a search value) to the gate voltage on the ML pulldown transistors.(c) When the input voltage is smaller than a threshold, the voltage on the gate of the T1 is large enough to pull down the match line (ML), yielding a 'mismatch' result.The threshold is tuned by the memristor conductance.(d) Similarly, when the input voltage is larger than a threshold, which is tuned by the second memristor conductance, the cell returns a 'mismatch' result by pulling down the ML.Here, SL hi is at 0.8V which sets the max G1 and G2 voltage.
different M1 and M2 memristor conductances (FIGURE 2c, d).As a result, the cell keeps ML high only when V DL is within a certain range as defined by the M1 and M2 conductances.As several cells are connected on the same ML in a row, just as in digital CAMs, a row ML outputs 'high' only when each cell in the row matches.

Simulations and experiments
We validated the operation of our memristor analog circuit with circuit simulations (see Methods for details) based on a layout using commercial 180 nm design rules.FIGURE 3a shows the layout with the required peripherals (such as on-chip pre-charging circuits) and an analog CAM array.The memristor conductance tuning in an analog CAM array is similar to the 'write' operation in a 1T1M array and described in the SUPPLEMENTARY SECTION 1.The current design prioritizes feasibility and demonstration of this new circuit concept, and is not yet optimized for speed or power consumption.
We first set the conductance of two memristors in one analog CAM cell to 50 µS and 100 µS and apply different V DL values to observe the changing V ML behavior during the search operation.
All other cells are programmed to the 'always match' or 'don't care' state, and therefore do not impact V ML .From simulations we see that after the search is initiated (by pulling SL hi high), V ML stays high (FIGURE 3b) when V DL is 0.6 V, indicating a 'match', but is discharged low when V DL is either 0.4 V or 0.8 V for a 'mismatch'.The operation timing diagram and voltage parameters are presented in SUPPLEMENTARY FIGURE 2. Therefore, the search result can be measured from the transient V ML at some time following the search when the voltage difference (i.e.sensing margin) between match and mismatch scenarios is large enough for a sense circuit.The simulated V ML value at 10 ns following the search operation for different V DL (FIGURE 3c) shows that this pro- grammed memristor configuration corresponds to matching for 0.53 V< V DL <0.65 V.The lower bound (V lo) and the upper bound (V hi) of the analog CAM cell's acceptable matching range can be configured independently by tuning the corresponding memristor conductance in the cell.Using the resulting mapping between the voltage bound and conductances (FIGURE 3d) as a guide, we configured analog CAM cells to match various voltage ranges (FIGURE 3e and SUPPLEMENTARY FIGURE 3) or eight narrower ranges (FIGURE 3f) for representing 3-bit discrete voltage levels.
The results show that the proposed analog CAM cell implements the desired functionality and can be used to search for both discrete levels, encoding multiple bits in a single cell, or for arbitrary analog voltage ranges to encode continuous values.
We experimentally verified the proposed analog CAM cell operation using 1T1M structures with a test point between the memristor and transistor (see FIGURE 4a and Methods), allowing us to measure the FIGURE 2c voltage divider sub-circuit.The memristor devices were integrated through a back-end-of-the-line (BEOL) CMOS process in our lab, with Ta/HfO 2 memristor devices 34 with a wide > 10 4 range of conductance tunability (FIGURE 4b) and a programming voltage ∼1 V (FIGURE 4c), enabling us to validate the simulations described previously.With memristor conductances programmed across this wide range, we measured the G1 voltage while sweeping V DL up from zero (FIGURE 4d).The relationship between the search lower bound and the memristor conductance is extracted and plotted in FIGURE 4e.Comparing experimental results (FIGURE 4d and 4e) to simulation (FIGURE 2c and 3d) shows qualitative agreement, and the operational memristor conductance range experimentally demonstrated more than meets the required range to encode 3-bits of information in this analog CAM cell.The relationship between an analog CAM cell's stored range for a match and the programmed memristor conductances can be understood by the series connected transistor and memristor voltage divider (see FIGURE 2c, 2d).During a search operation, the serial transistors in the divider are working in the triode regime, as the voltage drop across the transistor channel is fairly small.
Under this condition, V ML stays high when V DL follows EQUATION 1, with bounds from the lower bound M1 voltage divider and the higher bound M2 voltage divider.
where V TH , V TH,ML , V TH,inv are the threshold voltages of the transistor in the M1 voltage divider, the T1 pull-down transistor, and the inverter respectively.β (= ∂ G T /∂V DL ) is a constant coefficient in the transistor transfer function.G M1 and G M2 are the memristor conductances, which are linearly related to the accepted V DL for a match according to the above equation.This analysis is consistent with the results shown in FIGURE 3d and FIGURE 4e, with an exception when the memristor conductance is very small such that the transistor voltage drop is also small, requiring the addition of nonlinear effects to the equation.Under this assumption, we can scale up our simulations from single cells to large analog CAM arrays to predict performance.
Memristor analog CAM arrays While we have demonstrated single analog CAM cell operation in a small array, it is crucial to investigate whether large arrays can be operated without fatal degradation effects.Using extracted parasitic parameters from layout, we constructed analog CAM arrays with arbitrary numbers of rows and columns (see Methods) to study how the analog CAM performs with increasing array size.FIGURE 5a shows the simulation configuration, where the two memristors in all of the analog CAM cells are configured to 50 µS and 100 µS to accept V DL from 0.53 V to 0.65 V.All DLs are biased to 0.6 V, except for one column DL that is swept from 0.0 V to 1.0 V to observe how V ML changes.This single-bit mismatch is the worst-case scenario as it represents the situation where the mismatch V ML is closest to the match V ML behavior.Since all cells with V DL =0.6 V match, the V ML drop leading to a 'mismatch' is initiated by the cells in the column with the sweeping DL.Analog CAM arrays with two columns but an increasing number of rows show no change (FIGURE 5b,c) in V ML with additional rows (simulated up to 1024 rows), demonstrating negligible row-wise interference.
As expected even with conventional CAMs, increasing the number of columns can lead to a degradation of the V ML (FIGURE 5d) such that the acceptable search range is slightly changed.Our analysis shows that this results from the sub-threshold leakage current of the pull-down transistors (see SUPPLEMENTARY SECTION 3 for more details).Nevertheless, the results show that the change in the accepted voltage range is within 0.05 V, which is sufficient to separate eight discrete levels for 3-bit searching capability in a 72-column analog CAM array.
To address the issue of sub-threshold current leakage which limits the word length and the number of stored bits per cell, we propose to replace the standard ML pull-down transistor with volatile threshold switching (TS) memristors [35][36][37] .Our analog CAM cell is converted to a circuit that is composed of four transistors, two non-volatile memristors, and two volatile TS memristors, as shown in FIGURE 6a.In contrast to our above implementation using pull-down transistors to discharge the ML for a mismatch result, a search operation in this case starts with ML at ground, and the ML is charged up only for mismatch cases.The performance of the proposed cell is evaluated in simulation (see Methods), where the Verilog-A based volatile TS memristor model parasitic parameters.b, The sensed ML voltage with respect to the input voltage applied to the DL in arrays with an increasing number of rows (or words).High logic level on the ML indicates that the searching input matches the stored memory, where the lower and the higher bounds (V lo and V high) are labeled in the plot.c, With an increasing number of rows, the searching range of one cell in the array stays unchanged.d, On the other hand, it changes noticeably with an increasing number of columns.In the worst case, up to 50 mV change is observed in an array of 72 columns.This still allows the capability to store and search 3-bits of information per analog cell across the 72 columns, but going beyond this would be challenged by the present circuit.The volatile threshold switching memristors pull up the ML in the case of a mismatch, which replaces the pull-down transistors in the 6T2M circuit.b, The volatile memristor is a threshold switching device with a very sharp transition between states (e.g.1 mV/dec 35 ), therefore reducing column interference issues exposed in earlier simulations.c, The match line stays low only when the input pattern (V DL ) matches the stored range.The dashed line shows the signal after the match line sense amplifier output (V MLSO ), which inverts and converts the analog signal to a binary 'match' (high) or 'mismatch' (low) signal.d, Due to the much smaller ∂ G pu /∂V G , the cell promises the capability to store more accurate ranges and accordingly more bits of discrete levels (showing 16 levels).e, f The search operation with a simulated array of different word width.The programmed memristor configuration and the expected searching range is the same as that in FIGURE 5, but the searching range is altered less than 10 mV indicating the capability to store 5-bits of information, which is close to the precision limit of most non-volatile memristor devices.
is extracted from published experimental data 35 .FIGURE 6b shows t he simulated current-voltage (IV) curve for the TS memristor, from which one sees a significantly smaller sub-threshold swing than MOSFET transistors, thereby greatly decreasing the sub-threshold current leakage on the ML.
The ML voltage sensed at 50 ns after the search starts (FIGURE 6) shows a match for V DL between 0.53 V and 0.65 V (see SUPPLEMENTARY SECTION 4 for additional details).As with the previous analog CAM cell, the simulated analog cell can be configured to match different V DL ranges by programming different memristor conductances.FIGURE 6d shows the successful analog CAM cell with 16 discrete programmable matching states.Further simulations (FIGURE 6e and f) of the analog CAM arrays show that the change in the matching voltage range moves by less than 0.01 V with columns of up to 72, indicating the capability to store and search 5-6 bits of information, showing a significant improvement from conventional designs with pull-down transistors.

Discussion
The main advantages of our proposed analog CAM are the improvements in energy and area over existing digital approaches.To demonstrate the potential scale of these improvements, we compared our analog CAM approach with the digital-equivalent for the usecase of classifying Internet protocol (IP) packets, which is a common commercial application for CAMs 13 .
The ternary wildcard 'X' capability of TCAMs is frequently used to compress multiple table entries into one row in the IP routing look-up table, owing to the fact that most classifying ranges are continuous.With our proposed analog CAM that is able to store broad ranges, this look-up table can be further compressed.Analysis in the previous section suggested that one analog CAM cell is capable of searching 8-64 discrete levels, depending on the implementation.This enables compressed rows, where fewer cells are required to store the same number of bits of information.
Additionally, taking advantage of the range storage capability, fewer rows are also required than in a digital CAM/TCAM representation.A real example is given in SUPPLEMENTARY SECTION 5, which shows a 14x reduction in number of required cells (from conventional TCAM to 16 level analog CAM cells, further reduction is possible with improved analog CAM cells).In addition, with only six transistors in an analog CAM cell, and 16 in an SRAM-based TCAM cell, an overall 37× reduction in chip area (or increased memory density) is achieved as well as a similar reduction in dynamic power consumption as this is dominated by wire capacitances.Static power is also reduced due to the non-volatility of the memristor device.We anticipate additional benefits when analog rather than digital data is directly processed by our analog CAM. In

Memristor integration
The memristor is monolithically integrated on top of transistors that are fabricated in a commercial foundry under 2 µm technology node.The integration starts with a removal of native oxide on the surface metal with physical bombardment with argon ions.An about 100 nm palladium is then sputtered and patterned as the bottom electrode, followed by a atomic layer deposited 5 nm hafnium dioxide as switching layer and a sputtered 50 nm tantalum as the top electrode.The device stack is finalized by a sputtered 10 nm palladium for passivation and improved electric conduction.per block and capacitance of 1.9 fF between different analog CAM cells.The voltage stimulus is always applied to the nodes that are the furthest from the ML sensing node, so that the impact of the wire resistance is the most significant, i.e. the worst case scenario.

Electrical characterization
The electrical characterization is conducted with a semiconductor parameter analyzer (Keysight B1500A) and Cascade probe station under room temperature.The conductance programming is performed with quasi-static direct-current (DC) sweeps, and where the current through the device is limited and controlled by the series connected transistor.After programming, the memristor conductance is readout by applying a small voltage across the memristor with the series-connected transistor fully turned on.The search operation is conducted by applying and sensing voltages from the corresponding node to/from a source measurement unit (SMU) on the B1500A.
space are considered (e.g.128 bit for IPv6).Here, we restrict ourselves to this smaller example for comparison purposes.
First, we observe that the whole TCAM array described above for a range search can be replaced by a single 16-bit analog cell.Admittedly, it is challenging to realize a 16-bit analog CAM cell currently, but we've shown that it is very feasible for a 3-bit or 4-bit cell to be implemented, as demonstrated in FIGURE 3e,f.With limited bit-precision analog CAM cells, the range can be split in a similar way as in TCAM entries.SUPPLEMENTARY FIGURE 6b and SUPPLEMENTARY FIGURE 6c show implementations with 3-bit analog CAM and 4-bit analog CAM respectively.In the table, 'X' is similar to that in the TCAM, which matches everything, i.e. 0-7 in a 3-bit cell or 0-15 in a 4-bit cell.{n − m} represent the cell is configured to match part of the range between n and m.From the figure, one sees that by using a multi-bit analog CAM, both columns and rows can be compressed, leading to a reduction from 336 TCAM cells to 54 3-bit cells or 24 4-bit cells.
In addition, there are only six transistors in an analog CAM cell, while 16 in a SRAM-based one.
With these factors taken into consideration, the overall transistor count required for this specific function results in a 37× reduction in chip area.We also expect a similar reduction in operational power with the analog CAM cell in comparison to conventional TCAMs, as a major portion of the dynamic energy consumption for a CAM operation is charging parasitic wire capacitances, and the reduced cell count and area also results in shorter wires and reduces total wire capacitance.

Figure 1 :
Figure 1: Schematic of the memristor analog TCAM concept.a, A digital content-addressable memory

Figure 2 :
Figure 2: 6T2M analog CAM circuit.a, Schematic of our proposed analog CAM circuit, composed

Figure 3 :
Figure 3: Simulations of the memristor analog CAM.a, The layout design of one analog CAM cell in an analog CAM array with peripherals using commercial 180 nm design rules.The transistors in this proof-ofconcept design are over-sized to allow driving larger currents.b, Simulated transient voltage response on the ML where the different curves show searches with different data line (DL) voltages for a matching case (red) and two mismatching cases (blue, yellow).c, The circuit simulation with the same memristor configuration shown in (b) shows that the cell matches a range of DL voltage, whose bounds are independently controlled by the conductances of the two memristors in the cell.d, The simulated relation between the search range and the memristor conductance.The blue curve shows the lower bound of the range, while red shows the upper bound.e, f, Using differently configured memristor conductances, the cells in the array can store (e) a continuous range of values, or (f) discrete levels (showing eight levels or 3-bits).

Figure 4 :
Figure 4: Proof-of-principle experimental demonstration.a, An optical microscopic image of a mem-ristor integrated monolithically on top of silicon transistors.Scale bar, 4 µm b, The current-voltage relation of the memristor in the proposed analog CAM circuit for many programmed states, showing the wide continuously tunable conductance range.c, The conductance can be tuned from a low conductance state to a high conductance state by a large voltage (> 0.5 V) on SL hi, and reversely by a large voltage on SL lo.d, After configuring the memristor to different conductances, the experimentally measured gate voltage of the pull-down transistor (corresponding to G1 node in Fig.2c) drops below the threshold voltage with increasing voltage on DL.During the measurement, SL hi and SL lo is biased at 0.5 V and 0 V respectively.e, The boundary DL voltage for the analog CAM outputting a 'match' (i.e. the pull-down transistor stays off) increases with the programmed memristor conductance.Despite the different transistor size in this proof-of-concept experiment, the result qualitatively matches the simulation in FIGURE3d.

Figure 5 :
Figure 5: Analog CAM arrays.a, Simulated analog CAM arrays with different sizes using extracted

Figure 6 :
Figure6: An analog CAM circuit using both volatile and non-volatile memristors a, Schematic for our analog CAM circuit, composed of four transistors and four memristors (two non-volatile and two volatile).The volatile threshold switching memristors pull up the ML in the case of a mismatch, which replaces the pull-down transistors in the 6T2M circuit.b, The volatile memristor is a threshold switching device with a very sharp transition between states (e.g.1 mV/dec35 ), therefore reducing column interference issues exposed in earlier simulations.c, The match line stays low only when the input pattern (V DL ) matches the stored range.The dashed line shows the signal after the match line sense amplifier output (V MLSO ), which inverts and converts the analog signal to a binary 'match' (high) or 'mismatch' (low) signal.d, Due to the much smaller ∂ G pu /∂V G , the cell promises the capability to store more accurate ranges and accordingly more bits of discrete levels (showing 16 levels).e, f The search operation with a simulated array of different word width.The programmed memristor configuration and the expected searching range is the same as that in FIGURE5, but the searching range is altered less than 10 mV indicating the capability to store 5-bits of information, which is close to the precision limit of most non-volatile memristor devices.
summary, we have proposed an analog CAM cell circuit taking advantage of the analog memristor conductance tunability for the first time.A practical circuit implementation composed of six transistors and two memristors has been demonstrated in both experiment and simulation.The analog CAM increases memory density significantly, as one analog CAM cell can store multiple bits with only six transistors while an SRAM CAM cell stores 1 bit values with 10 transistors, or ternary values with 16 transistors in a TCAM cell.The analog capability opens up the possibility for directly processing analog signals acquired from sensors, and is particularly attractive for Internet of Things applications due to the potential low power and footprint.The output of the analog CAM after the sense amplifiers is digital, and thus can also remove the analog-digital conversion cost entirely.Finally, the functionality of our analog CAM with interval storage is intrinsically different from digital CAMs, which may enable new computing applications in fuzzy logic and probabilistic processing where inexact compares and real-valued analog transition probabilities are common.
Circuit simulation for analog CAM cell and arrays The proposed 6T2M analog CAM cells designed in the Cadence Virtuoso Custom IC design environment (version 6.1.7),and the simulation result is analyzed and post-processed with HP-SPICE (version 4.11).The simulations utilize the TSMC 180 nm library and the designs follow the corresponding rules.The voltage parameters and timing diagram are shown in SUPPLEMENTARY FIGURE 2. A custom python script generates the netlist for analog CAM arrays with different numbers of rows and columns and arbitrary configured memristor conductances and input voltages.In the netlist, the parasitic parameters are extracted from the taped out layout, including the wire resistance (for ML, SL, DL, etc) of 1.4 Ω