Is negative capacitance FET a steep-slope logic switch?

The negative-capacitance field-effect transistor(NC-FET) has attracted tremendous research efforts. However, the lack of a clear physical picture and design rule for this device has led to numerous invalid fabrications. In this work, we address this issue based on an unexpectedly concise and insightful analytical formulation of the minimum hysteresis-free subthreshold swing (SS), together with several important conclusions. Firstly, well-designed MOSFETs that have low trap density, low doping in the channel, and excellent electrostatic integrity, receive very limited benefit from NC in terms of achieving subthermionic SS. Secondly, quantum-capacitance is the limiting factor for NC-FETs to achieve hysteresis-free subthermionic SS, and FETs that can operate in the quantum-capacitance limit are desired platforms for NC-FET construction. Finally, a practical role of NC in FETs is to save the subthreshold and overdrive voltage losses. Our analysis and findings are intended to steer the NC-FET research in the right direction.

where P is polarization, E is electric field. Supplementary Figure 2a shows the Gibbs free energy landscape under different electric field. The circles represent stable (valley regions) and metastable (barrier region, indicated with green shade) P states for different values of E. By letting dU/dP = 0, a continuous P-E curve can be obtained, which includes all the possible polarization states of a FE material in response to an external electric field.
In this curve, there is a portion exhibiting negative P-E slope (Supplementary Figure 2b), which, in physics, represents a negative capacitance (NC) region 2 . The NC region corresponds to the barrier region in the energy landscape (Supplementary Figure 2a), which is metastable in an isolated FE system. It is worthwhile to note that the absolute value of the P-E slope is generally very large, i.e., the absolute NC dielectric constant | NC | is very large. For example, | NC | of the CMOS compatible Hf 0.5 Zr 0.5 O 2 , can reach ~ 75 0 , which is more than three times that of HfO 2 . It was predicted that by connecting a FE in series with a normal dielectric (DE) (Supplementary Figure 2c), with proper capacitance matching between FE and DE, i.e., |C FE | ≥ C DE , the stack energy can be stable 2

Supplementary Note 3: Detailed Derivations of Equations in Figures 2 and 4
The drain current of a (n-type) FET can be expressed as where W is device width, and v is carrier velocity, Q e is the electron charge density in the channel, All other symbols in this equation have the same meaning as that in Equation 2 in the main manuscript, and have been explained there. Note that quantum capacitance C Q is the first derivative of Q e w.r.t the channel potential and can be obtained from Equation 2 in the main manuscript.
The slope of the Where V g is the gate voltage, V MOS is the voltage at the interface of NC and oxide, and φ ch is the channel potential, as illustrated in Figure 1 in the main manuscript. According to the small-signal capacitor network shown in Figure 1b in the main manuscript, (∆V MOS -∆φ Ch )·C OX = ∆φ Ch ·C div , and (∆V g - ≈ 60 ade which stems from the thermionic emission transport mechanism.
As have been discussed in the main manuscript, in the near and above-threshold regimes, C Q dominates As have been discussed in the main manuscript, in the subthreshold regime of a poorly designed short-channel NC-FET, short-channel capacitance C SCE , which is mainly composed of source/drain geometry capacitance C s/d,geo , dominates C div , i.e., C div ≈C SCE , S TP =60, Equation S3d is reduced to infinitely large in the above equations, In the near-and above-threshold regimes, C div ≈C Q , then, In the subthreshold regime of a short-channel MOSFET, C div ≈C SCE , S TP =60, Equation S3e is reduced to produce a device with combined inheritance of good electrostatics and NC effect 11,12 . However, the merits of these modern/good FETs make the voltage divider capacitance C div,<Vth (=C trap +C dep +C s,geo +C d,geo ) negligibly small (Supplementary Figure 3a), thereby limiting their capability to benefit from NC. Also, many researchers may intuitively arrive at the conclusion that the UTB of modern MOSFETs can serve as a large channel capacitance or a large effective C dep (Figure 1 in the main manuscript) which, however, is a fundamental misunderstanding of FET physics. In UTB MOSFET, body terminal is absent, i.e., the other side (w.r.t. the gate) of UTB is electrically floating. Therefore, the thickness of UTB does not determine the channel capacitance or effective C dep . In fact, UTB suppresses C div,<Vth and hence C MOS,<Vth (=C OX From an NC operation point of view, subthreshold charge density Q MOS,<Vth (=C MOS,<Vth ·V g ) in these "good" FETs induces (through electric displacement field D (=C MOS,<Vth ·V g ), which is continuous across oxide/NC interface) negligible polarization in NC, and thus miniscule voltage gain in the main manuscript). Therefore, contrary to MOSFET design, a voltage divider (i.e., finite C div,<Vth ) should be intentionally introduced into NC-FETs to exploit A v benefits. It is worthwhile to note that a mid-gap trap density of ~110 11 cm -2 can introduce appreciable capacitance into C MOS,<Vth . In other words, NC benefit and steep slope may be more readily observable in devices in which defective materials such as 2D, organic, amorphous and polycrystalline materials, and poor interfaces such as III-V/Oxide and Ge/Oxide are involved, compared to high-quality Si devices.

Supplementary Note 5: Large Quantum Capacitance in MOSFETs
In FETs, quantum capacitance C Q describes the change of the mobile charges in response to channel potential modulation (Equation 2 in the main text). As shown in the simulation results in Supplementary   Figure 4, even in the ultrathin channel of a 5 nm UTB SOI MOSFET with EOT of 1 nm, C Q is still much larger than C OX .

Supplementary Note 6: Derivation of Minimum SS
As indicated in Figure 2d in the main manuscript, minimum SS (SS min ) that does not suffer from hysteresis can be obtained by matching |C NC | to C MOS,>Vth , i.e., by substituting |C NC | = C MOS,>Vth into the SS formula in Figure 2b in the main manuscript, According to Equation 3 in the main manuscript, C MOS,>Vth = C div,>Vth ·C OX /(C div,>Vth + C OX ), then Substituting C div,>Vth = C div,<Vth +C Q into above equation, we arrive at

Supplementary Note 7: The Effect of NC Non-Linearity
The linear term (with coefficient α) in Equation S2b, gives a constant (bias independent) ɛ NC =1/(dE/dP)+ɛ 0 =1/(2α)+ɛ 0 (and hence C NC ) as the 0 th order approximation (Supplementary Figure 5a), which is valid in low-to-medium electric-field range, as indicated in Supplementary Figure 2b. Note that α is negative, which is the source of negative capacitance. When electric field approaches the coercive field of FE (the two turning points in Supplementary Figure 2b), the nonlinearity terms (with β and γ coefficients) begin to deviate the P-E relation from linearity.
To simplify the analysis, γ coefficient is set to be zero in this work. As a result, |ɛ NC | (and hence |C NC |) increases with bias or charge density, as indicated by the derived formula in Supplementary Figure 5a.
This non-linearity introduces a damping term to the slopes of both SS/60 and S/S TP lines versus NC layer thickness T NC (Supplementary Figure 5b), which can be depicted as a counterclockwise rotation of both S/S TP and SS/60 lines, leading to enlarged NC design space, at the expense of increased SS, as illustrated in Supplementary Figure 5b. Supplementary Figures 5c and 5d show simulated I d -V g and S-I d characteristics of a Si SOI NC-FET (inset), respectively, with different non-linearity term β. With increased β, hysteresis is effectively eliminated, at the expense of increased SS, which is consistent with the uncovered role of NC non-linearity in Supplementary Figure 5b. Note that the simulation here is performed on a fixed device structure/size. With larger β, NC design space is wider, SS min can be lower if the device structure/size is optimized.
Note that although the effect of NC non-linearity on the design space of hysteresis-free SS has been discussed in a previous paper 13 , the clear physics picture developed in this work allows us to explain this matter much more effectively, in terms of clarity, depth, and generality.
It is worth mentioning that the appearance of multi-domains and/or poly-crystals, w.r.t the ideal single-domain case considered in this work, in the ferroelectric layer may introduce additional and unpredictable non-linearity, because these discrete domains/crystals are unlikely to have uniform properties (P-E curves). As well known, today's scaled transistors already get severely loaded by 'bias-dependent' capacitances such as gate-to-source/drain capacitances C g,s/d and Miller capacitance etc, which makes the device/circuit behavior difficult to be precisely evaluated. The multi-domain and poly-crystalline ferroelectric layer added in NC-FETs, not only further complicate the device behavior, but also serve as a major source of performance variation in short-channel NC-FETs that have comparable feature sizes w.r.t. these domains/crystals.

Supplementary Note 8: The Mechanism of Internal Metal Gate (IMG) Aided NC-FET
An internal metal gate (IMG) inserted between the NC layer and oxide has been found able to achieve small SS in short-channel FinFETs, without introducing hysteresis 14 . This section clarifies the underlying physics using the same analysis developed in the main manuscript. Supplementary Figure 6a shows the capacitor network in a NC-FET with IMG. It can be found that two additional fringing (overlapping included) capacitors, C frin,s/d-IMG , appear between source/drain and the floating IMG. S and SS formula are derived and revisited for this structure, as shown in Supplementary Figure 6b. In FinFETs, as have been discussed in the main manuscript and Supplementary Note 4, C div,<Vth → 0, thus

Note that the essential difference is that the additional C frin,s/d-IMG is in parallel with
In Interestingly, the NC design space (between 0 and 1/( C OX +C frin,s/d-IMG )) and SS min become irrelevant w.r.t.
C Q , and only dependent on C OX and C frin,s/d-IMG . This is because C frin,s/d-IMG provide parasitic charge in both subthreshold and above-threshold regime to induce polarization in NC, which unlocks the dependence of polarization on mobile charge (or C Q ) in "good" FETs. As indicated by the SS min formula, SS min can be effectively reduced by increasing the ratio of C frin,s/d-IMG to C OX , which perfectly explains the previous report that short-channel NC FinFETs with IMG can achieve small SS. Note that trap states can introduce appreciable C trap , and hence C div,<Vth . Even in such a thin film, C Q is still much larger w.r.t. the 1 nm SiO 2 gate oxide capacitance C OX . Note that C Q for 1 nm and 5 nm SiO 2 gate oxide will converge to the same value when V g keeps increasing, i.e., the maximum C Q is independent of gate oxide thickness. shows that with stronger NC non-linearity, i.e., larger β, the hysteresis is suppressed, but SS gets degraded, which is consistent with the uncovered NC non-linearity effects in a and b.

Supplementary
Supplementary Figure 6