Gate-controlled reversible rectifying behaviour in tunnel contacted atomically-thin MoS2 transistor

Atomically thin two-dimensional semiconducting materials integrated into van der Waals heterostructures have enabled architectures that hold great promise for next generation nanoelectronics. However, challenges still remain to enable their applications as compliant materials for integration in logic devices. Here, we devise a reverted stacking technique to intercalate a wrinkle-free boron nitride tunnel layer between MoS2 channel and source drain electrodes. Vertical tunnelling of electrons therefore makes it possible to suppress the Schottky barriers and Fermi level pinning, leading to homogeneous gate-control of the channel chemical potential across the bandgap edges. The observed features of ambipolar pn to np diode, which can be reversibly gate tuned, paves the way for future logic applications and high performance switches based on atomically thin semiconducting channel.

show strongly asymmetric V ds polarization in the whole gate range. Interestingly, when the tunnel bias voltage is larger than a threshold value of about +1 V, the device start to exhibit ambipolar transfer curves, with the hole side conductivity comparable, sometimes even larger than that of the electron side.
We recorded the gate leakage current (I leak ) from the bottom graphite gate concomitant with transport measurement, to rule out any such influence. It is confirmed that leakage current is limited in a sub 100 pA range, compared to the measured bipolar field effect curve giving I ds up to over 100 nA.
When at negative V ds , the transfer curves of TC-FETs become unipolar up to the highest tested gate range (Supplementary Figure 5), but still differs from conventional FET. After the turn-on point, I ds initially increases exponentially, and then enters a broad saturation plateau at higher electron doping. It is noteworthy that a shoulder toward saturation is often seen also on the electron side of the transfer curve at positive V ds , such as indicated in Fig. 2b in the main text.
We find that the amplitude of I ds -V g characteristics is dependent on the area of

Relaxation limits
The geometries are optimized until all residual force tolerance is smaller than 0.05 eV Å -1 . This relaxation limit follows the previous studies on the metal-MoS 2 contacts [4][5][6][7]. As mentioned in the previous section, we change the lattice constants in x direction of Au and h-BN to match the MoS 2 due to the sensitive influence of lattice structure on the band structure of MoS 2 .
Because the lattice constant in the x direction of h-BN is very similar to that of MoS 2 , we applied a 0.9% tensile strain of h-BN in x direction to make it match up with MoS 2 , while a 3.4% compression strain in the x direction is needed for the Au electrode to match with MoS 2 . Therefore, the distribution of strains in the system is mainly localized to the Au electrodes after relaxation. Although the compression strain will affect the electronic structure of Au electrode, the general metallicity cannot be changed. Therefore, the strains of Au electrodes have little effect on our calculation about the device's electronic transport properties. We adopted an energy cutoff of 150 Ry as in previous study of the Metal-MoSe 2 -Metal device [8]. Calculations with larger energy cutoff (180 Ry and 200 Ry) were also tested. The calculated results such as band gap of MoS 2 , transmission spectrum of normal-and tunnel-contacted device are similar to that of 150 Ry. Therefore, an energy cutoff of 150 Ry is eventually used in this work to achieve a balance between calculation efficiency and accuracy.

Tunneling barriers
To explore the effective barrier height of 2-layered h-BN, we calculated the average electrostatic potentials along y directions for each model in Supplementary It is known that the calculated gap of 1.8 eV is close to the value of optical gap of monolayer MoS 2 . If one takes into account the quasi-particle excitation in the simulations, the electronic band gap will be around 2.3-2.6 eV. Limited by the huge computational expense added by quasi-particle calculations, in this work we used conventional LDA functions without quasi-particle corrections. However, this should not affect the general transport behaviors simulated, as have been widely adopted and shown in previous studies [5,[10][11], where the LDA has been proven to yield rather

Further discussions on the IV curves in MoS 2 TC-FETs
We calculated the I-V characteristics of 1-layered h-BN TC-FET model, in which the calculated current density is 2-3 orders of magnitude higher than the 2-layered model as shown in Supplementary Figure 11a. However, the rectifying behavior was not found under gate voltages of, for example, V g =0 V. We notice that, experimentally, the chance to have exfoliated monolayer h-BN is extremely low, and the thinnest limit used in this work is 2-layered h-BN. Nevertheless, chemical vapor deposition (CVD) grown mono layer h-BN has been reported previously [12]. Their experimental observation showed no rectifying behavior when CVD grown monolayer h-BN is used as a spacing layer, probably due to a large amount of defects existing in the CVD h-BN.
On the other hand, Fig. 3i in the main text of our manuscript shows the I-V characteristics of 2-layered h-BN model at V g =3 V. One can see the current densities at bias voltage higher than 0.8 V show a saturation tendency, which is in good agreement with the experimental result. We further plot the intensity at higher voltage and the saturation of the current can be still observed up to 1.2 V, which can be found in Supplementary Figure 11b. We expect current saturation in even higher bias voltages, although calculation difficulty (poor convergence) at far from equilibrium condition prohibits us from further simulation.

Supplementary Note 4: Cut-off frequency of the MoS 2 TC-FETs
It is of importance to have an idea on the upper limit of frequency when the TC-FETs are still operating. During the measurement, output waveform was monitored in real time with an oscilloscope, while sweeping the frequency of the input sinusoidal waves. One can see in Supplementary Figure 12 that when the input wave frequency is reaching the order of 20 kHz, output curve starts to be distorted. In the mean time, de-phasing between input and output waves also starts to show above 20 kHz. We therefore define 20 kHz as a cut-off frequency of our MoS 2 TC-FET devices.
It is noteworthy that in a device directly fabricated on SiO 2 with the Si gate heavily doped, the parasitic capacitance between electrodes (typically over 100×100 µm 2 ) and the back-gate could be the limitation of the bandwidth of working frequency.
To reveal the physical cut-off frequency, one has to fabricate the devices on insulating substrates that are specially designed for high frequency tests.

Supplementary Note 5: Hysteresis measurements in the MoS 2 normal and TC-FETs
The use of tunnel-thin h-BN layer intercalated between the S/D contacts and It can be seen that the TC-FET shows as small hysteresis as that of normal MoS 2 FET, in both field effect curves and IV curves. This can rule out, in future applications, the reliability issues which could be caused by charge trapping between the h-BN and MoS 2 interfaces.

Supplementary Methods
It is known that in the fabrication process toward resist-free pristine van der