With the emergence of wearable or disposable electronics, there grows a demand for a flash memory realizable on various flexible substrates. Nevertheless, it has been challenging to develop a flash memory that simultaneously exhibits a significant level of flexibility and performance. This is mainly due to the scarcity of flexible dielectric materials with insulating properties sufficient for a flash memory, which involves dual dielectric layers, respectively, responsible for tunneling and blocking of charges. Here we report ultra-flexible organic flash memories based on polymer dielectrics prepared by initiated chemical vapor deposition. Using their near-ideal dielectric characteristics, we demonstrate flash memories bendable down to a radius of 300 μm that exhibits a relatively long-projected retention with a programming voltage on par with the present industrial standards. The proposed memory technology is then applied to non-conventional substrates, such as papers, to demonstrate its feasibility in a wide range of applications.
Flash memory is a non-volatile, transistor-based data-storage device that has become essential in most electronic systems found in modern daily life. With straightforward operation mechanisms and easy integration into NAND or NOR array architectures, flash memories have been established as by far the most successful and dominant non-volatile memory technology1, 2. Above all, their direct electrical programming requiring no mechanical parts greatly reduces the weight of an overall system as well as the power consumption, making it hugely popular in portable electronics spanning from thumb drives and memory cards to solid-state drives in smart phones and laptops1, 2. Emerging areas, such as wearable, body-attachable, or disposable electronics, will also greatly benefit from such characteristics of flash memories as well as from their well-established circuit infrastructure, provided that they can be realized on various non-rigid substrates and, at the same time, can exhibit a memory performance that is sufficient for real-world applications3,4,5,6,7,8,9,10,11,12. In these respects, many studies have been devoted to the development of flash memories based on organic or other emerging electronic materials that can potentially be compatible with flexible substrates13,14,15,16,17,18,19,20,21,22.
Despite promising demonstrations in the early stages13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36, however, the overall progress in this field has been far slower than that of thin-film transistors (TFTs) or other devices based on flexible materials37,38,39,40,41,42,43,44,45,46. Major challenges lie in the core structure of flash memories, which involves dielectric bilayers sandwiching a charge storage layer such as a floating gate (FG) electrode (Fig. 1a). In addition to playing a regular role as a gate insulator, these two dielectric layers have to provide a reliable and controllable means by serving, respectively, (i) as a tunneling dielectric layer (TDL) through which to inject charges into the FG for programming or to remove charges therefrom for erasing via control of a control gate (CG) bias; and (ii) as a blocking dielectric layer (BDL) to prevent charge leakage to confine the stored charges within the FG for memory retention and to ensure that charge flow occurs only through the TDL during programming/erasing (Fig. 1b)1, 2. For reasonably low-programming/erasing voltages, these dielectric layers should not be made too thick; this unfortunately contradicts the conditions for long memory retention in many cases. A best-case scenario would thus be to use dielectric layers that are thin enough to enable low-voltage programming/erasing and yet can provide leak-free insulating properties even at such small thickness. Finding such an ideal dielectric layer has been very difficult for polymeric layers, which are the most prominent candidate material for flexible electronics47,48,49,50. The solution processing used for most polymeric dielectric layers also makes it difficult to use them in flash memories due to the complexity involved in the formation of the bilayer dielectric structure, which is the key to flash memory operations. All of these considerations have made it highly challenging to realize true flash memories in flexible form factors.
Herein, we try to overcome these hurdles and realize highly flexible flash memories by employing thin polymeric insulators grown with initiated chemical vapor deposition (iCVD), a vapor-phase growth technique for polymers pioneered by Gleason and her coworkers51. With tunneling-limited characteristics, these dielectrics have recently been demonstrated as flexible gate insulators that are important for low-voltage flexible TFTs52. In this work, it is further shown that the iCVD-based polymeric insulators can make a significant contribution to flash memories as well. With a rational design and material choice that carefully consider both applied and built-in electric fields across the dielectric layers for each operating condition, the proposed approach simultaneously enables long retention (projected to be ~>10 years) and low-programming/erasing voltages comparable to the present industrial standards (~±10 V). We then take full advantage of the mild, solvent-free, and low-temperature growth of iCVD to demonstrate flexible flash memories on various non-rigid substrates including ultrathin plastics and paper.
Design and characterization of organic flash memories
The proposed non-volatile memory devices are based on C60-based organic TFTs, wherein the gate insulator is replaced with a TDL/FG/BDL, as shown in the schematic device structure presented in Fig. 1a. C60 was chosen mainly for its consistency that led to a mobility larger than 1 cm2 V−1 s−1 with a good run-to-run reproducibility53,54,55,56. Two iCVD processed polymer films of poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) and poly(ethylene glycol dimethacrylate) (pEGDMA)52, whose chemical structures are shown in Fig. 1c, are employed for TDL and BDL, respectively. While pV3D3 was chosen for its excellent insulating properties and down scalability that had previously been reported by Moon et al.52, pEGDMA was selected not only for its consistent insulating performance comparable to that of pV3D3, but also for its dielectric constant larger than that of pV3D3, which will be discussed later in details. As can be seen in the false-color high-resolution transmission electron microscopy (HRTEM) image in Fig. 1a, these polymers make a conformal coating on the bumpy Al surfaces used as a CG and a FG, respectively, thanks to the characteristics inherent to the vapor-based iCVD method. This conformal growth is highly beneficial in the present case because it can minimize a chance of forming accidental electrical short paths. Like pV3D352, pEGDMA polymer layers also have superb insulating properties even on flexible substrates, with low leakage current density (Ji) and a relatively high breakdown field of over 6 MV cm−1 (Fig. 2a). This is due not only to the conformal coverage but also to the tunneling-limited insulating properties of iCVD-based polymers, which are characteristic to near-ideal dielectric layers with low trap densities52. The tunneling-limited behavior can be verified from their Ji vs. applied electric field (Ei) characteristics, which are almost independent of the device temperature over a wide range, as shown in ref. 51 for pV3D3 and in Fig. 2b for pEGDMA.
From the viewpoint of memory operation, the Ji–Ei characteristics of a metal-insulator-metal (MIM) device with near-ideal dielectric layers may be divided into two distinctive regions as shown for pEGDMA in Fig. 2a: (i) a low-Ei regime where Ji is significantly low due to direct-like tunneling where tunneling should be made through a full barrier width; and (ii) a high-Ei regime where Ji exhibits field-enhanced behavior, due to Fowler–Nordheim (F–N)-like tunneling, which involves tunneling through field-induced triangular barriers. It should be noted that, in both regimes, each tunneling mechanism could be further assisted with trap-assisted tunneling (TAT) found in dielectrics like high-quality Al2O357, 58, where a localized trap can help the respective tunneling processes by playing a role like that of a “stepping stone.” Staying in the low-Ei region is important in terms of memory retention, while utilizing field-enhanced, F–N-like tunneling can become critical for programming and erasing. Hence, it is crucial to ensure the field across TDL (=ETDL) is high enough during programming/erasing so that Ji is dominated by F–N-like tunneling. On the other hand, the field across BDL (=EBDL) should always remain low to prevent charges from flowing through BDL in all the cases and to let charges flow into or out from FG only through TDL, if necessary for programming or erasing. To fulfill these seemingly conflicting conditions simultaneously, it is necessary to first look at the voltages across BDL (=VBDL) and TDL (=VTDL) and the associated EBDL and ETDL when a bias (=VCG) is applied to a CG with respect to a source (S) and drain (D) electrodes. EBDL and ETDL are linked to each other via the so-called coupling ratio (αCR = VFG/VCG) and thus depend on the properties of both BDL and TDL, rather than solely on the properties of their own dielectric layers. Consider, for simplicity’s sake, an S/TDL/FG/BDL/CG structure, which is equivalent to the memory structure underneath S electrode except for the absence of a semiconductor layer. Under capacitive approximation and in the absence of a built-in field, it can be shown that ETDL/EBDL scales with kBDLABDL/(kTDLATDL), where k i and A i (i = BDL or TDL) are the relative dielectric constant and area of the insulating layers under study (see Supplementary Fig. 1 and Supplementary Note 1 for further details). pEGDMA used as a BDL in this work was found to have a k value of 3.059, which is significantly higher than that of pV3D3 used as a TDL (=2.2). This tends to make it easy for the condition of ETDL > EBDL to be met at a given VCG for programming/erasing, and thus provides a foundation to realize the required asymmetry between carrier flows though BDL and TDL. It is noteworthy that the dielectric constant of parylene, a polymer produced from vapor phase and commonly used in many areas, is on par with that of pEGDMA. Hence parylene could also be used for a BDL in this scheme. One concern for parylene is, however, its relatively low break-down field60. Nevertheless, the report by Song et al. demonstrates that the dielectric properties of polymers could be significantly improved upon use of soft contacts such as transferred graphene61. If the break-down field of parylene can further be increased in this way, parylene may also be used as one of the gate dielectric layers for memory devices.
Once kTDL and kBDL are chosen, one needs to determine the thicknesses of BDL (=dBDL) and TDL (=dTDL) that can fulfill the field requirements for all the memory operation conditions. In the real memory structure (instead of the aforementioned simplified case), the detailed energy band alignment should be carefully taken into account, because it can lead to built-in fields across BDL and TDL and thus exert an influence on the net field across those layers. It should further be noted that the built-in fields vary depending on the memory state because they are influenced by the differential increase or decrease in the amount of charge confined within FG (see Supplementary Table 1 and description therein for further details). Another complication, which results from the inherent properties of a typical organic TFT, is the change in αCR associated with the dependence of the capacitance of the FG/TDL/channel/S(D) structure (=CTDL) on the operation modes. Due to the gate-modulated conductivity of the channel, the effective thickness and area determining CTDL during programming (i.e., channel is ON) are dTDL and the area underneath the channel that overlaps with FG, respectively; in contrast, those relevant to the erasing process (i.e., channel is OFF) are dTDL plus the channel thickness (dchannel) and the area underneath D and S electrodes overlapping with FG, respectively (Fig. 2c, d). The energy diagrams in Fig. 1b were constructed by considering the location of Fermi level for C60 and its interfacial alignment with Ca62, the spatial distribution of the vacuum level shift associated with the confined charges, the applied VCG (if any), and operation-mode-dependent αCR, etc. With a BDL thicker than a TDL (in this work, dBDL/dTDL = 1.8–5), energy diagrams are configured in such a way that F–N-like tunneling can occur efficiently across TDL, while it is much less effective for BDL due either to the low net electric field (during the programming operation; Fig. 1b “programming”) or to the energy barrier configuration, which is relevant to direct tunneling instead of F–N tunneling (during the erasing operation; Fig. 1b “erasing”).
When choosing dTDL and dBDL, it should also be kept in mind that these values should be larger than the critical thickness (=dcrit) of the corresponding dielectric layer, below which the layer’s insulating properties will quickly be degraded47, 63. A statistical study done for pEGDMA-based MIM devices fabricated in several batches indicates that dcrit of pEGDMA is ca. 30 nm (Fig. 2e). We have thus adopted the pEGDMA layer that is at least thicker than ca. 30-40 nm. With dcrit of pV3D3 being ca. 10 nm52, the total dielectric thickness can be maintained within 50–68 nm. With this total thickness, we were able to keep the programming and erasing voltages (Vprg and Vers) relatively low while still fulfilling all the requirements mentioned above. For example, the proposed flexible organic flash memory with 40 nm-thick pEGDMA and 16 nm-thick pV3D3 on PET substrates exhibited transistor characteristics that can be switched on at less than 3 V; the device also showed a sufficient voltage shift (ΔVth) of ~5 V with Vprg and Vers as low as ±10 V (Fig. 2f). Note that these levels of ΔVth and programming/erasing voltages are comparable to those of conventional Si-based flash memory devices2, 64. With |Δnfg| = CBDL × |ΔVth|/e, wherein Δnfg and e refer to the change in carrier density stored in FG and charge of an electron, respectively, the observed ΔVth corresponds to Δnfg of 2.1 × 1012 cm−2, which is on par with those of most flash-like memories found in the literature (see Supplementary Table 2). The reason why Δnfg exhibits little variation among different devices, albeit their widespread ΔVth, is that a flash memory with lower CBDL generally requires higher operating voltages and thus demands higher ΔVth for proper memory operation, making the CBDLΔVth product (and thus Δnfg) remain in the similar range among different systems. In addition, the flexible memory devices in this study showed reliable programming and erasing behaviors for repetitive operations of 1000 times (Fig. 2g and Supplementary Fig. 2).
Moreover, the proposed memory devices exhibited significantly long retention time (tret), estimated to be 3.2 × 108 s (≈10 years), during which over 50% of the initial ΔVth is projected to be preserved (Fig. 2h). As can be seen in the energy diagram given in Fig. 1b) for “Programmed state”, presence of the stored charges in FG tends to yield band bending in energy bands for both TDL and BDL. Because their slopes are still relatively small, however, the field across the insulators remain within the low-field regime. In this case, tunneling probability can be maintained low enough to enable long retention, provided that there are no other leakage paths such as electrical shorts. The observed level of large tret is thus consistent with tunneling-limited insulating properties of pV3D3 and pEGDMA used in this work. Nonetheless, one should keep in mind that the quoted retention time is the extrapolated value that considers only the electrical aspects and that the actual memory retention is subject to degradation depending on ambient conditions. The long-term test with proper encapsulation should be made to fully assess their actual retention time in practice. As for programming/erasing speed, the device showed a ΔVth of ca. 2 V at tprg and ters as low as 10 ms (Fig. 2i), simultaneously fulfilling all the requirements for key performance parameters—reasonably low voltage and short time span for programming and erasing; and sufficiently long retention.
Mechanical flexibility of the proposed organic flash memories
To estimate the mechanical durability of the proposed organic flash memory, a device fabricated on a 250 μm-thick PET substrate was tested as a function of flexural tensile strain by adjusting the bending radius of curvature. The device showed consistent programming/erasing behaviors after flexural deformation corresponding to tensile strain of up to 2.8% (Fig. 3a and Supplementary Fig. 3), and it still exhibited memory characteristics even after the 10,000 bending cycles at a flexural strain of 1.1% (Fig. 3b and Supplementary Fig. 4). This excellent mechanical durability against flexural strain can be attributed to the highly flexible nature of the iCVD-based polymeric dielectric layers. Both the pEGDMA and pV3D3 dielectric layers maintained their insulating property at tensile strain of up to 4% in a bending test using MIM devices (Fig. 3c, Supplementary Fig. 3, and refs. 51, 52. these results are in sharp contrast to the cases of inorganic dielectric layers that typically lose their insulating property with strain of ~1% in a similar test37.
It is noteworthy that the onset strain for failure (=εonset) is lower for flexible memory devices than for the corresponding flexible MIM devices. This is attributed to the relatively complex device structure of memory devices, which involves a larger number of heterogeneous interfaces than is present in MIM devices. This is consistent with the εonset value of 3.3% obtained for a C60-based TFT transistor having the same configuration as the proposed flash memory except that Al FG is not included (see Supplementary Fig. 5).
Even with a value of εonset smaller than those of the corresponding TFTs or MIM devices, the observed value is still unprecedented for flexible flash memories13,14,15,16,17,18 and is large enough to realize ultra-flexible form factors with a thin plastic substrate10, 37, 39. This will allow for a greater degree of freedom in designing flexible electronic systems, e.g., for wearable or skin-attachable electronic products. To verify this, the memory devices under study were fabricated on 6 μm-thick MylarTM films using 33 nm-thick pEGDMA as a BDL and 17 nm-thick pV3D3 as a TDL. As can be seen in Fig. 3d, the devices were easily bendable over a needle with the radius of merely 300 μm. The resultant devices show non-volatile memory operation comparable to that of the devices prepared on thick PET substrates. As the 6 μm-thick plastic substrate significantly reduces the bending-induced strain at its surface, the achievable bending radius can become so small that devices on top of it can almost be folded. When tested with a custom-designed bending machine that can define a sub-mm bending radius with the assistance of a rigid piano wire (Fig. 3e, f, Supplementary Fig. 6, and Supplementary Movies 1 and 2), these devices were shown to maintain their programming and erasing capabilities in the folded state as well as after 1200-time folding cycles (Fig. 3d, g) for a bending radius of 300 μm. This demonstrates their potential as nearly foldable and light-weight flash memory devices, which will be pivotal for epidermal or imperceptible electronics10, 37, 39. The possibility of fabricating these devices on MylarTM or PET substrates is a direct benefit of the low-temperature processability of the iCVD process, as these polyester films have relatively low-service temperature and glass-rubber transition temperature. Upon comparison with the previous works, the result shown here can be regarded as a significant breakthrough toward realization of highly flexible flash memory that satisfies both low Vprg, Vers, and long tret (Supplementary Table 2 and Supplementary Fig. 7).
Realization of flash memories on papers for disposable electronics
Another advantage of the iCVD process that can be useful for flexible memory devices is its solvent-free nature52, 65, 66. Together with the conformal coating capability and low-temperature processability, this benefit provides the potential to build memory devices on a wide range of unconventional substrates, including those with a low damage threshold to liquid as well as those with relatively large roughness52, 65, 66. In this respect, one attractive yet highly challenging substrate to build memory devices on is paper, which has all the unfavorable conditions mentioned above67,68,69,70,71,72,73,74,75,76,77,78,79. To determine whether substrates for the proposed memory can be extended even to paper, we built our devices on so-called dye-sublimation papers (DP), which has a significantly rough surface with bumps in both micro- and nano-scale (Fig. 4a, b and Supplementary Fig. 8). Note that DP does not have a plastic coating unlike the thick specialty photo paper used for inkjet printing of photographs. It was found that, thanks to the conformal coating capability of iCVD, a 111 nm-thick pEGDMA layer exhibited a considerable insulating property even on such a rough DP surface, as shown as a black line with squares in Fig. 4c. An organic flash memory fabricated on the DP surface with the 111 nm-thick pEGDMA-based BDL and a 44 nm-thick pV3D3-based TDL was shown to be successfully operable with ΔVth of ~13 V for Vprg or Vers of ±25 V (Fig. 4d).
To further drive down the operation voltage of memory devices on paper, we used the iCVD process to apply a 1.5 μm-thick poly(divinylbenzene) (pDVB) layer on the pristine DP surface so that nano-scale bumps were smoothened and only the relatively large micron-scale profiles remained. pDVB was chosen mainly for its relatively high deposition rate (~μm h−1) and, moreover, for its planarizing capability. (Fig. 4e, f and Supplementary Fig. 8) In this case, even a 44 nm-thick pEGDMA layer showed a sufficiently good insulating property that was on par with the property observed in devices on glass or plastic substrates, as can be seen as a red line with circles in Fig. 4c. With this modification, the organic flash memory with the 44 nm-thick pEGDMA BDL and a 24 nm-thick pV3D3 TDL showed non-volatile memory operation with ΔVth of ca. 8 V at Vprg or Vers of ±15 V (Fig. 4g, h). To the best of our knowledge, this is the first demonstration of the flash memories on paper with practically meaningful operation voltage and a sufficient memory window. The results clearly demonstrate the immense potential of the iCVD process for flash memories on almost any kinds of flexible substrates.
In summary, flexible organic flash memory devices realized in this work on various substrates exhibit both industry-compatible operating voltage (~10 V) and relatively long-projected retention time. Thanks to the virtue of iCVD-based polymeric insulating layers with a near-ideal insulating property limited by carrier tunneling, an organic flash memory can be designed, in a systematic fashion, based on a TDL/FG/BDL structure. The versatile synthetic capability of the iCVD process makes it possible to choose, from the pool of various iCVD-based polymers, a proper insulator that can meet the conditions that are key to the systematic design (e.g., a TDL with low dcrit; a BDL with a higher dielectric constant than a TDL). Furthermore, the advantages of the iCVD process, such as low process temperature, solution-free nature, and highly conformal deposition, help one to realize flash memories on various flexible substrates such as PET, ultrathin MylarTM, and paper, which would otherwise be highly challenging to build memory devices on. The proposed devices on thick PET substrates are found to be able to withstand flexural strain of up to 2.8%, which is unprecedented for non-volatile memory devices. It is noteworthy that the proposed approach is not specific to C60, which is known to be air-sensitive and thus subject to degradation without encapsulation; some of the air-stable compounds80, 81 can also be used provided that their preparation is compatible with flexible substrates of interest. All these advantages are expected to allow non-volatile memories to be fabricated on virtually any flexible substrates while maintaining a sufficient level of performance as well as a high degree of mechanical flexibility. We believe the proposed approach will open a path for forthcoming electronics that are expected to be ubiquitous in daily life by providing an effective means for wearable, foldable, or disposable electronics.
Initiated chemical vapor deposition process
Each of the monomers called ethylene glycol dimethacrylate (EGDMA), 1,3,5-trimethyl-1,3,5-trivinyl cyclotrisilo-xane (V3D3), and divinylbenzene (DVB) was vaporized and delivered to a custom-built iCVD reactor with the initiator, tert-butyl peroxide (TBPO) for the formation of pEGDMA, pV3D3, and pDVB, respectively, via free-radical polymerization reaction. The growth rates of pV3D3, pEGDMA, and pDVB were 1.5, 5, and 15 nm min−1, respectively. The process pressure was maintained at 70–300 mTorr, and the filament was heated to 160–200 °C. The substrate temperature was maintained at 40 °C. The thickness of the deposited polymer films was controlled in situ by a He–Ne laser (JDS Uniphase) interferometer system.
Surface and film characterization
To observe the cross-sectional structure of the non-volatile organic flash memory devices, the devices were sliced using a dual-beam focused ion beam (FIB, Helios Nanolab 450). HRTEM (Titan cubed G2 60-300) images were then obtained. The surface morphology of the bare dye-sublimation paper (DP) and the DP coated with pDVB was characterized using AFM (Nanosurf Nanite AFM & C3000 controller).
The glass substrates were cleaned with detergent dissolved in deionized (DI) water, DI water, acetone, and isopropyl alcohol (IPA) successively in an ultrasonic bath for 20 min each, and dried at 100 °C for 12 h in a vacuum oven. PET substrates were cleaned with IPA. Ultra-thin Mylar and DP substrates were not cleaned with solvent; instead, a stream of compressed N2 gas was just blown onto the substrates before fabrication.
For the planarization, PET and Mylar substrates were treated with air plasma (CUTE-1MP, Femto Science Inc.) for 1 min at 70 W. Directly after the plasma treatment, PET and Mylar films were spin-coated with a transparent photoresist (SU-8, Kayaku Microchem) at 2000 rpm (30 s).
For the fabrication of the bottom-gated C60-based non-volatile flash memory, 100 nm-thick Al as CG was deposited by thermal evaporation with a base pressure lower than 10−6 Torr using shadow masks with a deposition rate of ~0.1 nm s−1, and pEGDMA polymer insulators as the BDL were deposited by the iCVD process on the top of CG electrodes with the desired thicknesses. The 15 or 50 nm-thick Al as the FG was then thermally evaporated in the same manner as Al prepared for the CG. pV3D3 polymer insulators as TDL were then deposited by the iCVD process on top of the FG electrodes. The memory devices were then completed by sequential thermal evaporation of 50 nm-thick C60 channel layers (~0.07 nm s−1) and Ca (20 nm)/Al(100 nm) layers as source (S) and drain (D) electrodes. Patterns for electrodes were defined with shadow masks.
Electrical characterization of devices
All current density vs. voltage characteristics (J–V) were analyzed using a semiconductor parameter analyzer (HP4155A or HP4156C, Agilent). Electrical characteristics of any devices with C60 were measured under controlled atmosphere in an N2-filled glove box unless noted otherwise. Capacitance vs. voltage characteristics (C–V) of MIM devices were measured using a precision LCR meter (HP4284A, Agilent). Dielectric constants (k) were estimated by using the relationship among C, k, and thickness of an insulator, following the procedure described in “Methods” section in the previous work by Moon et al.52. To measure the J–V characteristics of the MIM devices with various values of device temperature (Tdev), the samples were placed on a hot chuck in a customized vacuum chamber with probe tips, and Tdev was systematically controlled by a combination of liquid N2 gas flow and the chuck heating. To evaluate the electrical properties of the flexible (or foldable) MIM and non-volatile memory devices as a function of the bending radius and the number of bending cycles, the devices were tested with a custom-built bending tester. In case of a sub-mm bending radius, a piano-wire was employed and held tightly to maintain a proper tension for straightness. For nearly foldable devices on MylarTM substrates, the center of the bending was carefully aligned to the center of individual MIMs and memory devices by using a microscope.
All relevant data supporting the findings of this study are included within the paper and its Supplementary Information File, or available from the corresponding authors on reasonable request.
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This work was supported by Samsung Research Funding Center of Samsung Electronics under Project Number SRFC-MA1402-04. H.M. is grateful to Brain Korea 21 Plus Program for post-doctoral fellowship.
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