P-type and n-type transistors are the basic elements for constructing silicon-based complementary metal-oxide-semiconductor (CMOS) electronics to realize digital and analog applications1. Typically, unipolar p-type and n-type transistors with high density are fabricated by various doping techniques and are integrated to build logic circuits2. The requirement of spatial separation in circuits makes the fabrication more complicated, resulting in the increase of fabrication costs. Conversely, ambipolar transistors, which can be easily switched between p-type and n-type by applying an electric field, are promising candidates to minimize circuit size with effectively simplified designs.

There are a few promising materials with the ambipolar property, including organic/inorganic semiconductors. However, organic semiconductors are rarely applied in high-frequency logic electronics due to the relatively low carrier mobility3. Graphene’s4 absence of bandgap hinders its application in logic devices, even though the bandgap can be somehow tuned5,6. Although layered black phosphate has been shown to possess a unique ambipolar property7, it hardly survives after several hours of exposure in the atmosphere due to the low reactive barrier between black phosphate and oxygen/water8,9,10. Recently, transition metal dichalcogenides (MX2, where M = group IVB–VIIB metal and X = chalcogen) with a layered crystal structure were demonstrated to exhibit excellent semiconducting electrical properties with a large on/off ratio11,12,13,14. Among them, tungsten diselenide (WSe2), which consists of one layer of W atoms sandwiched between two layers of Se atoms, has many excellent properties providing potential applications, including valley-based electronics15,16, spin-electronics, and optoelectronics17,18. More significantly, different from the unipolar n-type semiconductor MoS2 with the presence of sulfur vacancy and the strong Fermi level pinning near the conduction band19,20,21, WSe2 as an ambipolar semiconductor has been demonstrated as having Fermi level effectively shifting between the valence band and the conduction band under application of an external field22,23,24.

Recently, the optical and hole dominant transport properties of exfoliated WSe2 have been explored24,25,26,27. To facilitate the potential application of WSe2 in CMOS, it is essential to understand the underlying ambipolar hole and electron transport mechanisms. In this study, we obtain deep insight into the thickness-dependent electric field screening effect, and the interlayer coupling interaction is analyzed according to Thomas–Fermi theory. The thickness from 1 to 40 L and temperature-dependent ambipolar transport behavior of WSe2 transistors are studied systematically. Furthermore, the Fermi level shift of WSe2 under gate voltage is investigated to understand its ambipolar behavior by Kelvin probe force microscopy. Finally, ambipolar WSe2 transistors in analog circuits exhibiting gate-controlled phase change are demonstrated in practical application in two-dimensional (2D) electronics.

Materials and methods

Device fabrication

The WSe2 flakes were mechanically exfoliated from a bulk crystal onto an SiO2/Si wafer using adhesive tape. The FETs were fabricated on a single wafer using electron beam lithography, simultaneously exposing all of the devices with the same processing step to ensure uniformity. The source and drain electrodes (10 nm Ti/40 nm Au) were deposited by electron beam deposition with a deposit speed of 0.2 Å/s. Before electron beam evaporation, the samples were kept overnight under the high vacuum of the electron beam deposition system. All of the devices were deposited simultaneously to ensure the same conditions. Before measurement, devices were annealed under Ar (including 10% H2) at 200 °C for 2 h.


The Raman spectroscopy measurements were carried out with 514-nm, 1.0-mW laser excitation and ×100 objective (Renishaw inVia Raman Spectroscope, Sweden). High-resolution transmission electron microscopy (HRTEM) imaging was conducted using an FEI Talos F200X operated at 200 kV. EFM measurements were performed with a commercial atomic force microscopy (AFM) instrument (Dimension Icon, Bruker, USA) under ambient conditions. Commercial rectangular silicon cantilever coated with a Co/Cr layer with a resonant frequency of 75 kHz and a spring constant of 2.8 N/m (MESP, Bruker, USA) was used for electrostatic force microscopy (EFM) imaging. The tip radius of the magnetic tip is ~35 nm. The tip lift height is 10 nm. A Keithley 4200SCS was employed to measure the direct current transport properties of the devices using a probe station in a vacuum chamber. The performance of the analogs circuits was measured using an oscilloscope (Agilent Infiniti Vision 3000). Vbias and VDD were applied by the Keithley 4200SCS, and Vac was applied using a signal generator (Agilent 33120 A).

Results and discussion

WSe2 flakes were prepared by mechanical exfoliation, and the optical properties, including the optical contrast and Raman spectra, were characterized (see Supplementary Figures S1 and S2). As seen, the relationship between the optical contrast or Raman optical properties and thickness trends weaker and towards disorder when the layer number is higher than 4L. Furthermore, HRTEM was employed to study the atom-stacking mode of WSe2 with a thickness range from 1L to 12L (see Supplementary Figures S3 and S4). The similar properties, including the distance along (1̄010) or (01̄10) and the similar intensity profiles along the (1210), (0110), (1̄010), and (21̄10) directions in SAD patterns, indicate the same stack mode (2H mode) of WSe2.

To gain a deeper insight into the dimensionality effect on the interlayer screening in WSe2 flakes, EFM was employed to probe the electric field, which is caused by the charged impurities present at the WSe2/SiO2 substrate interface. In this study, the EFM measurements are conducted in a two-pass lift mode, in which a conductive AFM (c-AFM) cantilever first scanned over the WSe2 flakes for topography and then was lifted a constant height to detect long-range electric interactions between the voltage applied tip and WSe2 flakes. Because the EFM phase change directly relates to the unscreened charges, the observed differences in the EFM phase change indicate different field screening capabilities of WSe2 flakes with different thicknesses. The typical AFM topographic image of 1L and 2L WSe2 on SiO2 is shown in Fig. 1a, and the corresponding EFM images under a negative tip voltage and a positive tip voltage are shown in Fig. 1b, c. The correlated line profiles from Fig. 1a–c are shown in Fig. 1d, where one can see that the phase shift (Δφ) of WSe2 is always negative compared to a bare SiO2 substrate. Significantly, Δφ is dependent on both WSe2 thickness and the tip bias. If the AFM tip and WSe2 can be considered as an ideal capacitance, the EFM phase shift can be described as Eq. (1)28,29, where Q and k are the Q-factor and spring constant of the cantilever, C is the local capacitance between the tip and WSe2, Vtip is the applied DC voltage, and Vs is the effective surface potential.

$${\mathrm{\Delta \varphi }} = \frac{Q}{{2k}}\frac{{\partial ^2C}}{{\partial ^2z}}\left( {V_{{\mathrm {tip}}} - V_{\mathrm s}} \right)^2.$$
Fig. 1: The EFM phase image of WSe2.
figure 1

a The AFM height image of 1L and 2L WSe2 and the corresponding phase image measured by EFM. b Vtip = −4 V. c Vtip = +4 V. d The line profiles in (ac). e, f Second-degree polynomial fitting to the normalized EFM phase of 1L and 40L WSe2, respectively, under Vtip ranging from +6 to −6 V. g The surface potential dependent on the thickness layer, as well as fittings using 2D (blue) and 3D (red) nonlinear Thomas−Fermi theory. h The logarithmic scales of (g)

Typically, a fit between Vtip and phase can be achieved for both 1L and 40L WSe2 by using a second-degree polynomial (Fig. 1e, f). The deviations of the Vs values for the 1–40L WSe2 are summarized in Fig. 1g. As seen, the effective surface potential difference decreases as thickness increases, indicating the screening effect of WSe2 enhanced with the number of layers. To gain insight into the screening effect, nonlinear Thomas–Fermi theory is employed to understand the interlayer couple interaction. First, if the interlayer coupling interaction is excluded, the screening effect is parallel, following the 2D model, and then the surface potential difference can be described as Eq. (2)28,29.

$$\Delta {{V}}\left( {{D}} \right) = \frac{{2\pi \hbar ^2\sigma _0}}{{eN_{\mathrm s}N_{\mathrm v}m_{||}}}\sqrt {2\beta _0d} \frac{{1 - r_D}}{{\sqrt {1 - r_D^2} }},$$

where \({\mathrm{r}}_D = 1/{\mathrm{cosh}}\left( {D\sqrt {2\beta _0/d} } \right)\); ħ is the reduced Plank constant; σ0 is the charge density on the SiO2 substrate; Ns and Nv are the spin and valley degeneracies (Hs = Nv = 2); m|| is the in-plane effective mass; d is the interlayer spacing in WSe2; \({\mathrm{\beta }}_0 = e^2N_{\mathrm s}N_{\mathrm v}m_{||}/4\pi \varepsilon _0\varepsilon \hbar ^2\); and ε0 and ε are the vacuum permittivity and the dielectric constant of WSe2 (ε = 7)30, respectively. The blue lines in Fig. 1g, h show the 2D fitting, where σ0 is 1.2 × 1013 cm−2, m|| is 0.01me and me is the electron rest mass. According to the fitting, one can see that the screening effect follows the 2D model when the thickness is less than 2.4 nm (3L WSe2), suggesting a weak interlayer coupling interaction at lower thickness. However, the 2D fitting is hardly acceptable when the thickness increases further, indicating that the interlayer coupling interaction becomes strong. The three-dimensional (3D) fitting, considering interlayer coupling interaction, can be described as Eq. (3)28,29.

$${\mathrm{\Delta}} V\left( {{D}} \right) = \frac{1}{2}\left( {\frac{{6\pi^2\hbar^3}}{{N_{\mathrm s}N_{\mathrm v}{\mathrm {d}}m_{||}\sqrt {m_{\bot}} }}} \right)^{\frac{2}{3}}\left( {\frac{{25\beta _ \bot {\mathrm {d}}\sigma_0^2}}{{8e^2}}} \right)^{2/5}\\ \times\frac{{1 - r_D}}{{\left( {1 - r_D^{5/2}} \right)^{2/5}}},$$

where \(m_ \bot = \hbar ^2/2t_ \bot d^2\), \(t_ \bot = 0.2{\mathrm {eV}}\) (\(t_ \bot \): interlayer hopping parameter), \(\beta _ \bot = \left( {4e^2/5\varepsilon _0{\mathrm{\varepsilon }}} \right)\left( {N_{\mathrm s}N_{\mathrm v}{\mathrm {d}}m_{||}\sqrt {m_ \bot } /6\pi ^2\hbar ^3} \right)^{2/3}\), and rD can be numerically solved from Eq. (4):

$$\left[ {\frac{{25\beta _ \bot {\mathrm d}\sigma _0^2}}{{8\left( {1 - r_D^{5/2}} \right)}}} \right]^{ - 1/10}\mathop {\smallint }\limits_{r_D}^1 \frac{{{\mathrm d}u}}{{\left( {u^{5/2} - r_D^{5/2}} \right)^{1/2}}} = \sqrt {\frac{{2\beta _ \bot }}{d}} D.$$

The red line in Fig. 1g, h shows the 3D fitting, where σ0 = 0.8 × 1013 cm−2 and m|| = 0.01me, respectively. One can see that the 3D fitting has much better consistency with the EFM results, particularly for the thicker region, indicating that WSe2 is mostly in a strong coupling regime, which will apparently be reflected in the electrical transport mechanism.

In order to explore the thickness-dependent transport behavior of WSe2, back-gated field effect WSe2 transistors (FETs) were fabricated, where Ti/Au instead of traditional p-type Pd/Au or Pt/Au contacts were deposited to form ambipolar contact. Figure 2a shows the optical image of the 12L WSe2 transistor. The transfer curve at room temperature (RT) is shown in Fig. 2b, indicating a typical ambipolar transport behavior, where the hole is the dominant carrier when VGS < −15 V and the electron is the dominant carrier when VGS > +15 V. The ambipolar behavior results from the shifting of the Fermi level under the electric field, which is attributed to the weak Fermi-level pinning at the metal/WSe2 interface. Figure 2c shows the gate voltage-dependent field effect mobility, which is calculated by μ = (L/WC0VDS)(dIDS/dVGS), where C0 is the capacity and L and W are the channel length and width, respectively. The maximum hole mobility and electron mobility are 196 and 150 cm2/V s when the gate voltage is −56 and +70 V, respectively. The balanced electron and hole transport characteristic results from the similar n-type and p-type Schottky barrier because Fermi level is closer to the middle level between the conduction band and valence band. Figure 2d, e shows the thickness-dependent results for hole mobility and electron mobility, where the mobility is extracted in both positive/negative 50–60 V ranges of gate voltages for hole mobility (μh) and electron mobility (μe), respectively. With the dimensionality increase from 2D (monolayer) to 3D (12L), both hole mobility and electron mobility increase. The mobility increase should be related to both the increased density of state inducing a smaller Schottky barrier (discussed later in Fig. 3d) and the screened interfacial charged impurities inducing a weaker scattering31. Moreover, the bandgap of WSe2 decreases as the thickness increases32, which is also one of the key reasons for the enhancement of electrical performance.

Fig. 2: The electrical properties of WSe2 transistors with different thicknesses.
figure 2

a The typical optical image of the device. b, c The electrical transfer curve of 12L WSe2 and the corresponding mobility, respectively. The channel length (L) is 8 μm. d, e The hole and electron mobility of WSe2 with thickness ranging from 1L to 40L. f The ratio of hole to electron mobility calculation from d and e. The error bars in df are from different devices

Fig. 3: The low-temperature electrical properties of WSe2 transistors with different thicknesses.
figure 3

a, b The electrical transfer properties of 1L and 7L WSe2 transistors under low temperature, and the inset is the corresponding hole and electron mobility dependent on the temperature. The channel lengths of the 1L and 7L WSe2 transistors are 3.3 and 1.4 μm, respectively. The transfer properties of other WSe2 transistors with different thicknesses are shown in Figure S5. c The ratio of hole to electron mobility of WSe2 as a function of the temperature. d The Arrhenius plots for different back gate biases of the 7L WSe2 device. e The Schottky barrier heights for different back gate biases of 1L, 7L, and 12L WSe2 devices

When the thickness is 40L, both the hole mobility and electron mobility decrease to ~20 cm2/V s, which should be caused by the increased series resistances associated with an increasing number of interlayers33. Fig. 2f shows the thickness-dependent μh/μe, which is the important factor for evaluating the symmetric transport characteristic. The ratio of μh/μe for 1L WSe2 is approximately 0.1, indicating an electron dominant transport characteristic, which implies that the hole carrier is almost suppressed by the interfacial charged impurities and has a more sensitive response than that of the electron carrier. For 2L and 3L WSe2, the ratio of μh/μe is approximately 3 and further increases to ~30 for 6L and 7L WSe2, which should result from the fast increase of hole mobility attributed to the screened interfacial charged impurities (Fig. 1). From 7L to 12L, the ratio of μh/μe decreases to approximately 1, corresponding to the balanced ambipolar transport behavior, which should result from the faster increase of μe (Fig. 2e) caused by the lower Schottky barrier height for the electron injection. In a 40L WSe2 transistor, the ratio of μh/μe is ~1, which suggests that the transport properties for the hole and electron carriers are same. The transport behavior (n-type or p-type) is not only dependent on the interfacial state but also dependent on the work function of metal contact. For the interfacial state, in combination with the EFM results (Fig. 1), we can propose that the channel region with thinner thickness has a higher effect from the interfacial charged impurities, and thus the hole carrier is suppressed, inducing n-type behavior. As the thickness increases, the interfacial charged impurities are screened, which makes the WSe2 flakes display intrinsic property. Alternately, the metal contact is also another critical role in transport. Pudasaini et al.34 reported that the carrier type can evolve from p-type to ambipolar to n-type in WSe2 using Cr (the work function of Cr is 4.6 eV) contact with increasing channel thickness. In thinner WSe2, the hole conduction appears dominant because the aligned Fermi level of thinner WSe2/Cr contact is below the middle of the bandgap. In this study, the lower work function of Ti (~4.3 eV)35 and the higher Schottky barrier height in the hole transport region can induce the preferential electron dominant conduction in thinner WSe2. This phenomenon is in line with the previous reported preferential n-type in thinner WSe2 with low-work-function metals, such as Ni, In, and Ag24,35. The requirement for real application of ambipolar semiconductor is not only the balanced hole and electron carrier but also the higher carrier mobility. Although the ratio of μh/μe in 2L WSe2 is close to 1, the electron mobility and hole mobility are relatively lower. Thus, the balanced hole and electron transport with higher mobility could be achieved in 12L WSe2, which could satisfy the requirement for practical ambipolar application.

To gain insight into the ambipolar transport behavior, the electrical properties of WSe2 transistors with different thicknesses are measured from RT to 5 K. The typical transfer curves of 1L and 7L WSe2 are shown in Fig. 3b (others are shown in Supplementary Figure S5). As seen in the 1L WSe2 transistor, the hole branch is almost completely gone, meaning that it is an insulator when the temperature decreases to 210 K, while the electron branch still exists. Interestingly, it is 60 K when the hole branch is fully suppressed in the 2 L WSe2 transistor. Further, in the 7 L WSe2 transistor, it is obviously seen that both the hole and electron branches exist until the temperature cools to 5 K. The corresponding temperature-dependent mobility is inserted, where one can see that the electron mobility slightly increases and then decreases, while the hole mobility rapidly decreases during cooling. The electron mobility shows a peak attributed to the dominant scattering switching from phonon scattering to charged impurities scattering during cooling. This phenomenon is also observed in electron-dominant back-gated MoS2 transistors36. Alternately, the hole mobility is monotonously and rapidly decreasing during cooling, implying that both the phonon and charged impurities scattering strongly effect the hole carrier, which is in line with the hole-dominant graphene transistor37.

Figure 3c shows the ratio of μh/μe as the function of temperature in WSe2 transistors with thickness ranging from 1L to 12L. We would simply separate the dominant transport mechanism by μh/μe = 1 as shown by the dashed line in Fig. 3c, and thus, the dominant carrier is the hole when μh/μe > 1, while the dominant carrier is the electron when μh/μe < 1. In 1–7L WSe2 transistors, the ratios of μh/μe almost decrease with temperature, which should be caused by the faster decrease of hole mobility originating from the relatively stronger scattering on the hole carrier compared to the relatively weaker scattering on the electron carrier. In detail, the ratios of μh/μe for WSe2 transistors monotonously decrease across the dashed line for 2L, 3L, 5L, and 6L at 280, 267, 228, and 80 K, respectively, which means that the dominant carrier is switched from hole carrier to electron carrier during cooling. The different converted temperatures in WSe2 transistors with different thicknesses are possibly attributed to their different scattering levels. Different from 1L–6L WSe2 transistors, the ratio of μh/μe for the 7L WSe2 transistor decreases from ~15 at 300 K to ~1 at 80 K and then saturates to 1. The hole and electron mobility as a function of temperature is shown in the inset of Fig. 3b, where the hole mobility decreases faster than the electron mobility. When the temperature is lower than 80 K, both the hole and electron mobility trend toward saturation, which is distinct from the evolution of hole and electron mobility in 1L–6L WSe2, where hole conduction rapidly decreases or even disappears. Therefore, from 7L WSe2, the electronic transport behavior trends toward an intrinsic property, whereby the dominant scattering is originated from the scattering center of the material rather than from interfacial charged impurity. Finally, the ratio of μh/μe in the 12L WSe2 transistor is approximately 1, implying that the influence of scattering on the hole or electron carrier is similar. The 12L WSe2 transistor with balanced ambipolar behavior originates from the bulk effect since the interfacial charged impurities are screened.

As known, the mobility behavior of a 2D material at low temperature is correlated with the contact metal but more significantly dependent on the scattering mechanism. Coulomb scattering originating from the interfacial charged impurity is one of the key scattering mechanisms. Although the interfacial charged impurity can be screened by introducing high-k dielectric, ion-gel, and BN23,27,36,38, the complex fabrication and higher cost need to be taken into consideration. Interestingly, the hole branch in the 1L WSe2 transistor disappears, suggesting that the effect of interfacial charged impurities on the hole carrier is much stronger than that on the electron carrier, while the interfacial charged impurity is screened in the 7L WSe2 transistor and leads to a similar effect on hole mobility and electron mobility.

Even for the samples that have be held in high vacuum overnight before electron beam evaporation, the TiOx buffer layer between Ti/Au contact and WSe2 may also be formed39,40, which will induce the formation of dipoles and further tune the Schottky barrier height. Thus, the transport property cannot be predicted by simple band offset, and, therefore, it is worth estimating the Schottky barrier to further reveal the thickness-dependent band profile. To evaluate the Schottky barrier height between metal and WSe2, IDS could be defined by 2D thermionic emission (Eq. (5)) due to its sufficiently thin channel41.

$$I_{\mathrm {{DS}}} = A_{{\mathrm {2D}}}^ \ast T^{3/2}{\mathrm{exp}}\left( {\frac{{\phi _{\mathrm B}}}{{k_{\mathrm B}T}}} \right)\left[ {1 - {\mathrm{exp}}\left( {\frac{{eV_{\mathrm {{DS}}}}}{{k_{\mathrm B}T}}} \right)} \right],$$

where \(A_{\mathrm {2D}}^ \ast\) is the 2D equivalent Richardson constant, T is the absolute temperature, kB is the Boltzmann constant, and ϕB is the effective Schottky barrier. The temperature dependence of the IDSVBG curve could be re-plotted with Arrhenius formation \(\left( {{\mathrm{ln}}\left( {I_{\mathrm {{DS}}}/T^{3/2}} \right)\sim 1000/T} \right)\) as shown in Fig. 3d (7L WSe2). The effective Schottky barrier could be obtained from the slope of the Arrhenius plot. Figure 3e shows the effective Schottky barrier as a function of the gate voltage of 1L, 7L, and 12L WSe2 devices. A peak between −10 and 0 V in the 7L WSe2 device is attributed to the opposite polarities of Schottky contact, which could be tuned based upon the gate voltage41. As seen, the effective Schottky barrier for the hole carrier is strongly dependent on the gate voltage compared to that for the electron carrier. Knowingly, the effective Schottky barrier for the hole is obviously reduced as the WSe2 thickness increases, while there is no noticeable change in the electron carrier. The above study demonstrates that 12L WSe2 exhibits good ambipolar behavior with balanced carrier mobility in a broad temperature range from RT to low temperature.

The above study reveals that the carrier of WSe2 can be effectively switched between electron and hole by a tunneling external electric field, corresponding to exhibit n-type and p-type behaviors, respectively. To reveal the ambipolar behavior of WSe2, the work function change and Fermi level shift of WSe2 are studied under different gate voltages. Here, in situ Kelvin probe force microscopy (KPFM) is employed to measure the contact potential difference between the tip and the sample, VCPD, which is referred to as the surface potential (VSP)42. To reduce the unscreened effect of gate voltage on the AFM cantilever, the gate electrode with a size of 20 µm is buried under the SiO2 layer. The WSe2 flake is transferred on the surface, and then source/drain electrodes are fabricated by electron beam lithography, as shown in Supplementary Figure S6. Figure 4a shows the schematic diagram of the setup for surface potential measurement, where the electrostatic force between the cantilever and sample is nullified by applying a DC bias.

Fig. 4: The Fermi level shift under an external electric field in ambipolar WSe2.
figure 4

a The schematic diagram for measuring the surface potential of WSe2 under an external electric field. The inset shows the optical image of the device, where a micro-scale buried gate electrode is fabricated to eliminate the effect of gate voltage on the AFM cantilever. The scale bar is 10 μm. b Transfer characteristics of the ambipolar WSe2 transistor. c The AFM morphology and corresponding surface potential map under zero gate voltage. The scale bar is 2 μm. d The surface potential of WSe2 under different gate voltages along the white line in c. e The surface potential on the Au electrode and WSe2 region as a function of gate voltage. The inset shows the different surface potentials of WSe2 and the Au electrode as a function of gate voltage. f The work function of WSe2 as a function of carrier concentration. The inset shows the corresponding shift of Fermi level

Figure 4b shows the transfer characteristic of the WSe2 device exhibiting typical ambipolar behavior. The charge neutrality point is located at 12 V, which is due to the interfacial state between WSe2 and sputtered SiO2. The height and corresponding surface potential of the device are shown in Fig. 4c. The line profiles under different gate voltages along the white line in Fig. 4c are shown in Fig. 4d. As seen, the shift of the background is due to the unscreened electrostatic interaction between the AFM cantilever and the buried gate voltage43. It has been reported that the gate voltage will not influence the surface potential of a metallic electrode; therefore, the background signal could be subtracted to obtain the relative surface potential change of WSe2, as shown in Fig. 4e. The surface potential difference ΔVSP between WSe2 and the Au electrode can be calculated by \(\Delta{V}_{\mathrm{SP}} = {V}_{{\mathrm{SP}\_{WSe}_{2}}}-{V}_{{\mathrm{SP}\_{Au}}}\), where \({V}_{{\mathrm{SP}\_{WSe}_{2}}}\) and \({V}_{{\mathrm{SP}\_{Au}}}\) are the surface potentials of WSe2 and Au, respectively. As seen in Fig. 4e, ΔVSP changes from ~−0.330 to ~0.100 V when the gate voltage varies from −14 to 28 V. A sudden change of ΔVSP (Fig. 4e) is observed at the charge neutrality point (VD), where the gate voltage is 12 V. The rapid change of ΔVSP is also reported in graphene, which may be related to the different electronic structures of the valance band and conductive band43. As known, the surface potential recorded by the KPFM could be formatted by \({eV}_{\rm{SP}} = \emptyset_{\it{tip}}-\emptyset_{\it{sample}}\), where \(\emptyset_{\it{tip}}\) and \(\emptyset_{\it{sample}}\) are the work functions of the AFM tip and sample42, respectively. Thus, the surface potential change is related to the work function: \({e}\Delta{V}_{\rm{SP}} = \emptyset_{\it{Au}} - \emptyset_{{WSe}_{2}}\), where \(\emptyset_{\it{Au}}\) and \(\emptyset_{{WSe}_{2}}\) are the work functions of Au and WSe2, respectively. Here, we assume that the work function of Au is 5.1 eV44,45, and therefore, the work function of WSe2 could be directly calculated by \(\emptyset_{{\mathrm{WSe}}_{2}} = \emptyset_{\mathrm{Au}} - e{\Delta} {V}_{\mathrm{SP}}\). Figure 4f shows the work function of WSe2 \(\left(\emptyset_{{\mathrm{WSe}}_{2}}\right)\) as a function of carrier concentration, where the carrier concentration is calculated by \({n} = {C}_{0} ({V}_{\mathrm{GS}} - {V}_{D})/{e}\). For this particular device, it is seen that \(\empty_{{\mathrm{WSe}}_{2}}\) could be tunneled by ~440 meV when WSe2 switches between n-type and p-type transport behaviors. Namely, the Fermi level will upshift by 100 meV when the WSe2 transmits from an insulator to an n-type semiconductor and downshift by 340 meV when the WSe2 transmits from an insulator to a p-type semiconductor, as shown in the inset of Fig. 4f.

As studied above, the WSe2 transistor displays typical ambipolar behavior with reasonable electron mobility and hole mobility, which has the potential for practicable use in communication7. As proof of the concept, the 12L WSe2 transistor is employed to demonstrate two basic functions of analog circuits. The schematic of the WSe2 amplifier is illustrated in Fig. 5a, where the supply voltage VDD is set to 3 V, and the off-chip resistor Rload is 10 kΩ. As seen, the gate voltage (VGS) is hence equal to the sum of a fixed DC bias voltage (Vbias) and a small sinusoidal AC signal (Vac, VPP = 10 V, f = 1 kHz). The DC transfer curve of the WSe2 transistor at RT is shown in Fig. 5b, which displays balanced electron and hole transport. The output signal (Vout) of the WSe2 amplifier is monitored on an oscilloscope as shown in Fig. 5c, d, corresponding to negative and positive Vbias, respectively. When a negative Vbias is applied to the WSe2 amplifier (Fig. 5c), in the positive phase of Vac, Ids increases/decreases as VGS decreases/increases, so the voltage drop across the off-chip resistor will increase/decrease, respectively46,47. As a consequence, the corresponding Vout will decrease/increase, which exhibits the same phase as the input signal. This situation is called the common-drain mode. Similarly, when Vbias is positive in the n-type branch, the corresponding Vout will increase/decrease as VGS decreases/increases, respectively, which exhibits a phase difference of 180° compared to Vac (Fig. 5d). This situation is called the common-source mode. Therefore, it is clear that the working mode of the WSe2 amplifier could be easily controlled by DC bias voltage. Two fundamental modes in a single WSe2 transistor demonstrate that one can develop other WSe2-based complicated analog circuits for signal processing performance with simplified circuit designs.

Fig. 5: The electrical performance of the WSe2 amplifier.
figure 5

a The schematic for the WSe2 amplifier. b DC transfer characteristics of the ambipolar WSe2 transistor. The channel length and width are 6.5 and 13.0 μm, respectively. c WSe2 amplifier in the common-drain mode, and the output signal shows the same phase as the input signal. d WSe2 amplifier in the common-source mode, and the output signal shows a 180° phase shift compared to the input signal. VDD and Rload are set to 3 V and 10 kΩ


In summary, EFM is employed to investigate the electric-field screening effect of WSe2 with a thickness range of 1–40 layers. The effective surface potential as a function of thickness is investigated in combination with non-linear Thomas–Fermi theory. The results show that the dielectric screening behavior follows a 2D model when the thickness is less than 3L, while it follows a 3D model when the thickness is greater than 3L. Significantly, the electrical transport properties of WSe2 transistors demonstrate that the WSe2 transistor exhibits ambipolar behavior and the asymmetric transport characteristic with different layer thicknesses. By studying the thickness- and temperature-dependent transport behavior, we successfully demonstrate that 12L WSe2 exhibits balanced ambipolar behavior with higher electron and electron mobility from RT to low temperature. Furthermore, the ambipolar behavior of WSe2 is studied by in situ KPFM to reveal its work function change/Fermi level shift as a function of gate voltage. The results show that the work function/Fermi level will be tunneled by 440 meV when WSe2 switches between n-type and p-type WSe2. Finally, the analog circuit composed of ambipolar 12L WSe2 transistors exhibits good controlled-phase performance, demonstrating its practical communication application in 2D electronics.