a In the frep locking circuit, the output of the MLL, whose frep is close to 250 MHz, is first detected by a detector; the fourth harmonic of frep is filtered out by a bandpass filter (BPF), amplified by a low-noise amplifier (LNA) and filtered again by another BPF. Then, the amplified and cleaned 4frep signal is mixed with another RF signal at frequency f1 from RF synthesizer 1. The output of the mixer is sent to a proportional integral (PI) controller to generate an error signal, which is fed back to a piezoelectric actuator (PZT), to lock frep to f1/4. b In the fceo locking circuit, the output of the MLL is amplified by an erbium-doped fiber amplifier (EDFA) and goes through a highly nonlinear fiber to generate a supercontinuum spectrum from 1000 to 2100 nm. The supercontinuum signal is launched into a periodically poled lithium niobate (PPLN) waveguide to double the frequency component from ~2040 to 1020 nm. The temperature of the PPLN is stabilized to 160 °C by a temperature controller (TEC). The original and new generated 1020 nm signals are filtered out by an optical BPF and beaten in a detector to obtain fceo, which is amplified and cleaned by an LNA and two BPFs. Then, the signal is divided by 25 and compared with f2 from RF synthesizer 2 in a digital phase detector (DPD). The output of the DPD is sent to a PI controller to generate an error signal, which is fed back to control the pump current of the MLL, to lock fceo to 25f2. c In the TL-to-comb locking circuit, the beat note of the MLL and the TL is first amplified and cleaned by an LNA and two BPFs; then, it is divided by 16 and compared with f3 from RF synthesizer 3 in a DPD. The output of the DPD is fed back through a PI controller to control the phase shifter of the TL to lock the frequency of the TL to one comb line of the MLL with an offset frequency of 16f3.