Main

Synchronized sources, where current I is related to frequency by I=N e f and N is the integer number of electrons injected in one period, are the prime candidates for the devices to define one ampere in quantum metrology. The accuracy of these devices is based on the discreteness of the electron charge and the high accuracy of frequency determined from atomic clocks. Modern methods are replacing classical definitions of electrical quantities; voltage can be derived on the basis of the a.c. Josephson effect of superconductivity12 and resistance by the quantum Hall effect13,14, but one ampere still needs to be determined via the mutual force exerted by the leads carrying the current. Early proposals of current pumps for quantum metrology were based on arrays of mesoscopic metallic tunnel junctions5,6, in which small currents could eventually be pumped at very low error rates7. However, these multijunction devices are hard to control and relatively slow15. Thus, the quest for feasible implementation with a possibility of parallel architecture for higher yield have led to alternative solutions such as surface-acoustic-wave-driven one-dimensional channels8, superconducting devices11,16,17,18,19,20,21 and semiconducting quantum dots22. These do produce large currents in the nano-ampere range but their accuracy is still limited.

Surprisingly, a simple hybrid single-electron transistor, with a small normal-metal (N) island and superconducting (S) leads, has been overlooked in this context. As demonstrated here, an SNS transistor, or alternatively an NSN transistor, see Fig. 1, presents a robust turnstile for electrons showing current plateaux at multiples of e f. We emphasize here that a one-island turnstile does not work even in principle without the hybrid design. An important feature in the present system is that hybrid tunnel junctions suppress tunnelling in an energy range determined by the gap Δ in the density of states of the superconductor, see Fig. 1d bottom inset; current through a junction vanishes as long as |VJ|≲Δ/e.

Figure 1: The hybrid turnstile and its basic characteristics.
figure 1

a, An electron micrograph of an NSN turnstile. It is a single-electron transistor fabricated by standard electron beam lithography. The leads are made of copper metal (N) and the island, the small grain in the centre, is superconducting aluminium (S). In the SNS turnstile, the roles of aluminium and copper are swapped, that is the leads are superconducting and the island is normal-state. The measurement configuration is added to this image: d.c. bias voltage V is applied across the transistor, and a voltage composing of d.c. and a.c. components acts on the gate electrode. b, A magnified image of the island, indicating notation in c. For an equivalent SNS device, the labels N and S are interchanged.c, A basic pumping cycle of the turnstile. The normalized gate voltage ng≡CgVg/e, and the instantaneous charge number n on the island are shown in the top panel against time over one period. The bottom frame shows the relevant tunnelling rates, in units of Γ0≡Δ/(e2RT) through junctions J1 (left one) and J2 (right one), respectively. Besides the dominant forward processes, the two most important backward rates are shown. The tunnelling occurs when Γ is of order frequency f. Note that when it takes place for instance through junction J2 in the charge state n=0, the island transits into the n=−1 state, and the system stays in this state for a while because all of the tunnelling rates for the n=−1 state are vanishingly small right after this event. In one full cycle, one electron is transferred through the turnstile from left to right. d, Current–voltage (I V ) characteristics measured at various values of d.c. gate voltage with no a.c. voltage applied. The separation of the extreme I V curves is a signature of the charging energy EC=e2/(2CΣ), where CΣ is the total capacitance of the island. The arrow marks the working point in the turnstile experiments unless otherwise stated. The top inset shows a magnification of the I V within the gap region demonstrating high subgap resistance of above 10 GΩ. The lower inset shows the energy diagram for one junction biased at a voltage VJ. Normal metal is to the left of the barrier in the centre, and the superconductor to the right, with forbidden states within the energy interval 2Δ around the Fermi level.

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Figure 1a shows the simple electric configuration to operate a hybrid turnstile. A d.c. bias voltage V is applied between the source and drain of the transistor, and a voltage Vg with d.c. and a.c. components at the gate. In general, a sinusoidal a.c. gate voltage is superposed on the d.c. offset such that the total instantaneous voltage on the gate, normalized into charge in units of e, reads ng≡CgVg/e=ng0+Agsin(2πf t) at frequency f. Here, Cg is the capacitance of the gate electrode to the transistor island. In a basic operation cycle of Fig. 1c, we have chosen the gate offset ng and amplitude Ag to be ng0=Ag=0.5, and the bias voltage across the transistor is set at V =Δ/e to suppress tunnelling errors, as will be discussed below. The key point in the operation of the hybrid turnstile is that the charge state locks to a fixed value in any part of the operational cycle except at the moment when a desired tunnelling event occurs. This originates from the interplay of the superconducting gap in the energy spectrum and Coulomb blockade of single-electron tunnelling. It renders this structure to work as an accurate turnstile where errors can be suppressed efficiently by decreasing the temperature and by choosing the bias point properly within the superconducting gap. This locking mechanism is shown and explained in Fig. 1c for one operational cycle. On the contrary, in the biased NNN transistor with Coulomb blockade alone, non-synchronized almost frequency-independent d.c. current through the device is observed. Likewise, a corresponding fully superconducting SSS device is not favourable either, because the inevitable supercurrent of Cooper pairs induces significant leakage errors23.

Figure 2 shows the current through the SNS turnstile under varying parameters ng0,Ag and V. Figure 2c shows cross-sections of the three-dimensional plot of the type of Fig. 2a along different constant values of ng0 against the gate amplitude Ag. The corresponding prediction based on sequential tunnelling theory1 is shown by the dashed lines in the same plot. The experimental data follow the theoretical prediction very closely with wide flat plateaux at I=N e f. The magnitude of the pumped current is robust against fluctuations in relevant parameters. It is not sensitive to the exact dimensions or symmetry of the device, operational temperature, gate offset or its amplitude, or the exact form of the driving signal in general. Some of these dependencies are demonstrated in Fig. 2d based on our present measurements.

Figure 2: Measured characteristics of the SNS turnstile.
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a, Current plateaux I=N e f at f=12.5 MHz as a function of d.c. gate offset and a.c. gate amplitude. The diamond structure is shown up to N=10 steps. b, The plateaux at f=20 MHz as a function of the bias voltage V across the transistor up to the gap threshold of about 400 μV, see Fig. 1d. Current is shown here in a three-dimensional plot at different d.c. gate offset positions with a constant gate amplitude Ag=0.5. c, Current at V =200 μV measured at various values of d.c. gate offset and as a function of gate amplitude Ag (solid lines), f=20 MHz. d, The N=1 plateau measured at f=20 MHz around the centre of each diamond as a function of d.c. gate offset, a.c. gate amplitude and bias voltage V across the turnstile, respectively, from top to bottom. The dashed lines in c and the red solid lines in d show the theoretical results according to the sequential tunnelling model. Here, we have used the parameter values RT=350 kΩ and EC/kB=2 K from the d.c. I V curves (Fig. 1d), and an electron temperature of 80 mK. We further used Δ=185 μeV and subgap leakage of 2.5×10−4 of the asymptotic resistance. The dashed line in the bottom panel of d has a slope of 10 GΩ, suggesting that the measured slope here and that of the d.c. I V curve in Fig. 1d have the same origin. All of the measured currents in this letter have been multiplied by the same factor (1.004) for the best consistency with the model: this is well within the ±2% calibration accuracy of the gain of the current preamplifier used.

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Figure 3a shows the I V curves measured for ng0≃Ag≃0.5 at various frequencies. The frequency dependence of the current corresponding to the first plateau in measurements of the type that were shown in Fig. 2b is plotted in Fig. 3b against e f in the frequency regime up to 80 MHz. The predicted I=e f relation is followed closely within smaller than 1% deviations in absolute current throughout this range. We stress here that in the present measurement, using just a room-temperature current preamplifier, we cannot test the agreement between the prediction and the absolute value of the measured, relatively small current to a higher degree than this.

Figure 3: The frequency dependence of the SNS turnstile operation.
figure 3

a, I V curves measured at different frequencies ranging from 0 to 20 MHz, at gate settings corresponding to the centre of the first (N=1) current plateau. b, The measured current at the centre of the N=1 plateau at the fixed bias of V =200 μV. Linear dependence up to 80 MHz corresponding to I≃13 pA can be seen.

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Next we discuss the choice of the operating conditions of a hybrid turnstile and the potential accuracy of this device. Within the classical model of sequential single-electron tunnelling, the bias voltage V across the turnstile is a trade-off: small bias leads to tunnelling events in the backward direction and large V to errors due to replacement of the tunnelled charge by another one tunnelling in the forward direction through the other junction. Unwanted events of the first type occur at the relative rate of ≃exp(−e V /kBTN), where TN is the temperature of the normal-metal electrodes. Errors of the second type occur at the relative rate of ∼exp(−(2Δ−e V)/kBTN). The prefactor of this expression is of the order of unity in relevant cases of interest. Minimizing these errors thus yields e V ≃Δ, which is chosen as the operation point in the experiments. At this bias point, the two errors are of the order exp(−Δ/kBTN). For Δ≃200 μeV (aluminium) and TN<100 mK, that is, a standard range of operation temperature, we obtain a thermal error rate of ∼10−10, which is sufficiently small compared with the requested ∼10−8 accuracy of the metrological source4.

The analysis above neglects several types of error. High operation frequency is one source of error: it leads to missed tunnelling events and to enhanced tunnelling in the wrong direction. For charging energy EC∼Δ, these errors are suppressed approximately as exp(−Δ/2πf e2RT). With typical parameters, Δ for aluminium and RT=50 kΩ, we then request f≪4 GHz for accurate operation. Such a small value of RT seems acceptable because of sufficiently strong suppression of co-tunnelling effects in this system as will be discussed below. With exponential suppression of errors in f, the metrological accuracy limits the frequency to ∼100 MHz for turnstiles with aluminium as the superconductor. A possible way to increase the speed of the device is to use another superconductor with a larger gap, for example, niobium. With ultrasmall junctions, to keep EC∼Δ, which is another criterion to satisfy in order not to miss any tunnelling events at the chosen bias point, we would be able to increase the frequency and thus the synchronized current. This is an attractive yet unexplored possibility. Further improvement, about a factor of three increase in frequency, could be achieved by shaping the a.c. gate voltage to have a rectangular waveform.

Another source of potential errors is the co-tunnelling24, that is, higher-order quantum tunnelling processes, which limit the use of short arrays in normal-metal-based devices25. In an SNS turnstile, the lowest-order quasiparticle co-tunnelling errors are, however, suppressed ideally to zero within the superconducting gap. Another process of the same order that is not suppressed by the superconducting gap is the tunnelling of Cooper pairs, also called Andreev reflection. In junctions without pinholes in the barriers, the rate ΓA of this tunnelling should be quite small, , where Γ0≡Δ/(e2RT) and the effective number of the transport modes in the junction of area A can be estimated to be (refs 26,27,28). If the charging energy is large, EC>Δ, it suppresses direct tunnelling of Cooper pairs. Analysis shows that the lowest-order process that limits the accuracy of the hybrid turnstiles with ideal superconducting electrodes is then the co-tunnelling of one electron and one Cooper pair, the rate ΓCPE of which can be estimated roughly as . These processes can be suppressed efficiently by a proper choice of device parameters.

Subgap leakage, due, for instance, to non-zero density of quasiparticle states within the gap, introduces a material- and fabrication-specific source of errors into our system. This effect is demonstrated by the non-vanishing slope of the I V curve in the top inset of Fig. 1d and by an equal slope in the bias dependence of the bottom panel in Fig. 2d showing the current on the first plateau. The parabolic gate offset dependence around ng0=0.5 is likewise caused by leakage. Our estimates show that as far as co-tunnelling is concerned, such errors are smaller than those measured in the present devices. For sequential tunnelling, subgap leakage causes a substantial extra contribution to the current, of the order of 10−3 in the present device. With high-quality tunnel junctions, possibly by an improved fabrication process, its influence can be suppressed further. Furthermore, the separation of the current plateaux, with only one bias polarity, is in principle not sensitive to this effect, unlike the absolute value of current on a single plateau. Yet the subgap leakage is the main issue to be solved to realize a metrologically compatible turnstile. We would also like to point out that a series connection of a few SN junctions would present an improved version of a multijunction electron pump6,7 in terms of leakage and co-tunnelling errors, because this device can be operated without external bias voltage.

The charge transport in these systems is associated with non-trivial heat flux: on the basis of the same strategy as discussed here, a single-electron refrigerator can be realized29. In this device the superconductor is always heated, but under proper bias conditions heat flows out from the normal metal. Therefore, in a single-island realization, an SNS configuration is more favourable, as compared with the NSN turnstile. With quite realistic parameters it is possible to refrigerate the small, thermally well-isolated N island of an SNS turnstile substantially, and hence the error rates can be further suppressed. For example, with the parameters of the present sample but in the SNS configuration, the island would cool from 100 mK down to 70 mK on the first current plateau when pumping at 20 MHz frequency. The source and drain leads can be thermalized close to the bath temperature by a proper choice of geometry and materials. Another difference between the SNS and NSN structures is the role of the parity effect in the NSN turnstile, in which the pumping cycle leads to unavoidable excitation of at least one odd quasiparticle in the central S electrode, limiting the ultimate turnstile accuracy. Such a limitation should be absent in the SNS case.

One of the key advantages of the single-island turnstile, as compared with multi-island pumps, is that the influence of the background charges30 can be compensated by adjusting just a single d.c. gate voltage. Therefore, the level of the current can be increased by a relatively straightforward parallelization of several turnstiles. If an enhancement in current by, for example, an order of magnitude is necessary, the d.c.-gate settings of each of the ten turnstiles can be adjusted individually, whereafter their currents can be combined. The whole device can then be operated with common-to-all d.c. bias and a.c. gate drive.

Methods

Several hybrid turnstiles with aluminium as the superconductor, copper as the normal metal and aluminium oxide as the tunnel barrier in between were fabricated by standard electron beam lithography. Both the aluminium and the copper films were 50 nm thick. The charging energy of the aluminium island is EC/kB≃2 K. The sum of the tunnel resistances of the two junctions is 700 kΩ, that is, 350 kΩ per junction on average. The current–voltage (I V) characteristics of the transistor are shown in Fig. 1d at various values of the d.c. gate voltage and with no a.c. gate voltage applied. The superconducting gap suppresses the current strongly in the bias region |V |≲0.4 mV. Outside this region, the typical gate modulation pattern shows up2. The charging energy of the device was determined on the basis of the envelopes of these I V curves. The turnstile experiments were carried out by voltage biasing the transistor at V ≃Δ/e, highlighted by an arrow in Fig. 1d.