Skip to main content

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

  • Commentary
  • Published:

Memory leads the way to better computing

A Correction to this article was published on 05 August 2015

This article has been updated

New non-volatile memory devices store information using different physical mechanisms from those employed in today's memories and could achieve substantial improvements in computing performance and energy efficiency.

This is a preview of subscription content, access via your institution

Relevant articles

Open Access articles citing this article.

Access options

Buy this article

Prices may be subject to local taxes which are calculated during checkout

Figure 1: Memory hierarchy and various memory types.
Figure 2: A comparison of a key attribute (write energy versus device size) of emerging non-volatile memories.
Figure 3: Monolithic 3D integration of memory interleaved with logic computation layers.

Change history

  • 08 July 2015

    In this Commentary originally published, in Fig. 2 all data for STT-MRAM were too low by a factor of 10, and the lowermost data point for RRAM was a miscalculation of the original data in A. Chen, et al. IEDM 746–749 (2005); it should have appeared at 900 nm2, 12 pJ. Corrected in the online versions.

References

  1. Shulaker, M. et al. Monolithic 3D integration: a path from concept to reality http://www.date-conference.com/conference/session/9.8 (2015).

  2. Kogge, P. (ed.) ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems (DARPA Information Processing Techniques Office, 2008); http://www.cse.nd.edu/Reports/2008/TR-2008-13.pdf

    Google Scholar 

  3. Itoh, K. VLSI Memory Chip Design (Springer, 2001).

    Book  Google Scholar 

  4. Borkar, S. & Chien, A. W. Commun. Assoc. Comput. Machin. 54, 67–77 (2011).

    Google Scholar 

  5. http://www-03.ibm.com/press/us/en/pressrelease/20209.wss

  6. http://www.hgst.com/science-of-storage/about-hgst-research/innovation-timeline

  7. http://www-03.ibm.com/ibm/history/exhibits/storage/storage_350.html

  8. Brewer, J. & Gill, M. (eds) Nonvolatile Memory Technologies with Emphasis on Flash: A Comprehensive Guide to Understanding and Using Flash Memory Devices (Wiley/IEEE, 2011).

    Google Scholar 

  9. Qureshi, M. K., Srinivasan, V. & Rivers, J. A. SIGARCH Comput. Archit. News 37, 24–33 (2009).

    Article  Google Scholar 

  10. Parkin, S. S. P. Proc. Int. Electron Devices Meeting (IEDM) 903–906 (2004).

  11. Freitas, R. F. & Wilcke, W. W. IBM J. Res. Dev. 52, 439–447 (2008).

    Article  Google Scholar 

  12. Burr, G. W. et al. IBM J. Res. Dev. 52, 449–464 (2008).

    Article  Google Scholar 

  13. Kent, A. D. & Worledge, D. Nature Nanotech. 10, 187–191 (2015).

    Article  CAS  Google Scholar 

  14. Khvalkovskiy, A. V. et al. J. Phys. D 46, 74001 (2013).

    Article  Google Scholar 

  15. Morris, D., Bromberg, D., Zhu, G-J. & Pileggi, L. Design and Automation Conf. (DAC), 49th ACM/EDAC/IEEE 486–491 (2012).

    Google Scholar 

  16. Datta, S., Salahuddin, S. & Behin-Aein, B. Appl. Phys. Lett. 101, 252411 (2012).

    Article  Google Scholar 

  17. Bhowmik, D., You, L. & Salahuddin, S. Nature Nanotech. 9, 59–63 (2014).

    Article  CAS  Google Scholar 

  18. Wong, H.-S. P. et al. Proc. IEEE 98, 2201–2227 (2010).

    Article  Google Scholar 

  19. Yamada, N. et al. Jpn. J. Appl. Phys. 26, 61–66 (1987).

    Article  Google Scholar 

  20. Liang, J., Jeyasingh, R. G. D., Chen, H-Y. & Wong, H.-S. P. IEEE Trans. Electron Devices 59, 1155–1163 (2012).

    Article  CAS  Google Scholar 

  21. Takaura, N. et al. VLSI Technol Symp. T130–T131 (2013).

    Google Scholar 

  22. Waser, R. & Aono, M. Nature Mater. 6, 833–840 (2007).

    Article  CAS  Google Scholar 

  23. Wong, H.-S. P. et al. Proc. IEEE 100, 1951–1970 (2012).

    Article  CAS  Google Scholar 

  24. Kamiya, K. et al. Phys. Rev. B 87, 155201 (2013).

    Article  Google Scholar 

  25. Prince, B. Vertical 3D Memory Technologies (Wiley, 2014).

    Book  Google Scholar 

  26. Waser, R., Dittmann, R., Staikov, G. & Szot, K. Adv. Mater. 21, 2632–2663 (2009).

    Article  CAS  Google Scholar 

  27. Zahurak, J. et al. Int. Electron Devices Meeting (IEDM) 140–144, Paper 6.2 (2014).

    Google Scholar 

  28. Lai, S. & Lowrey, T. Int. Electron Devices Meeting (IEDM) Paper 36.5 (2001).

    Google Scholar 

  29. Bette, A. et al. Digest of Technical Papers: 2003 Symp. VLSI Circuits 217–220 (IEEE, 2003).

    Google Scholar 

  30. Akerman, J. Science 308, 508–510 (2005).

    Article  CAS  Google Scholar 

  31. http://www.cccblog.org/2012/05/29/21st-century-computer-architecture

  32. Zhu, Q. et al. IEEE 23rd Int. Conf. Application-Specific Systems, Architectures Processors (ASAP) 125–132 (2012).

    Google Scholar 

  33. Shulaker, M. et al. Nature 501, 256–530 (2013).

    Article  Google Scholar 

  34. Wang, H. et al. Int. Electron Devices Meeting (IEDM) 88–91 (2012).

    Google Scholar 

  35. https://nano.stanford.edu/stanford-memory-trends

  36. Ebrahimi, M. S. et al. SOI-3D-Subthreshold Microelectronics Technology Unified Conf. (S3S) 1–2 http://dx.doi.org/10.1109/S3S.2014.7028198 (IEEE, 2014).

    Book  Google Scholar 

Download references

Acknowledgements

The authors acknowledge support from the National Science Foundation Center for Energy Efficient Electronics Science, STARnet FAME, LEAST, and SONIC Centers, IARPA, and member companies of the Stanford Non-Volatile Memory Technology Initiative (NMTRI) and the Stanford SystemX Alliance. Discussions with S. Mitra, M. Sabry, C. Kozyrakis, K. Olukotun, L. Pileggi, F. Franchetti, J. Rabaey and J. Bokor, as well as technical assistance from our students are gratefully acknowledged.

Author information

Authors and Affiliations

Authors

Corresponding authors

Correspondence to H.-S. Philip Wong or Sayeef Salahuddin.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Wong, HS., Salahuddin, S. Memory leads the way to better computing. Nature Nanotech 10, 191–194 (2015). https://doi.org/10.1038/nnano.2015.29

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1038/nnano.2015.29

This article is cited by

Search

Quick links

Nature Briefing

Sign up for the Nature Briefing newsletter — what matters in science, free to your inbox daily.

Get the most important science stories of the day, free in your inbox. Sign up for Nature Briefing