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Silicene field-effect transistors operating at room temperature

Abstract

Free-standing silicene, a silicon analogue of graphene, has a buckled honeycomb lattice1 and, because of its Dirac bandstructure2,3 combined with its sensitive surface, offers the potential for a widely tunable two-dimensional monolayer, where external fields and interface interactions can be exploited to influence fundamental properties such as bandgap4 and band character5 for future nanoelectronic devices6,7. The quantum spin Hall effect3, chiral superconductivity8, giant magnetoresistance9 and various exotic field-dependent states7 have been predicted in monolayer silicene. Despite recent progress regarding the epitaxial synthesis of silicene8,9,10 and investigation of its electronic properties11,13,14,15, to date there has been no report of experimental silicene devices because of its air stability issue16. Here, we report a silicene field-effect transistor, corroborating theoretical expectations regarding its ambipolar Dirac charge transport17, with a measured room-temperature mobility of 100 cm2 V–1 s–1 attributed to acoustic phonon-limited transport18 and grain boundary scattering. These results are enabled by a growth–transfer–fabrication process that we have devised—silicene encapsulated delamination with native electrodes. This approach addresses a major challenge for material preservation of silicene during transfer and device fabrication and is applicable to other air-sensitive two-dimensional materials such as germanene2,3,4 and phosphorene19,20. Silicene's allotropic affinity with bulk silicon and its low-temperature synthesis compared with graphene or alternative two-dimensional semiconductors suggest a more direct integration with ubiquitous semiconductor technology.

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Figure 1: Schematics of silicene and its synthesis–transfer–fabrication process.
Figure 2: In situ materials characterization of silicene synthesis.
Figure 3: Monitoring air stability of Ag-supported silicene by Raman spectroscopy.
Figure 4: Silicene FET device.
Figure 5: Room-temperature electrical characterization of silicene transistor devices.

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Acknowledgements

This work is supported in part by the Army Research Office (contract W911NF-13-1-0364), the Southwest Academy of Nanoelectronics (SWAN) centre sponsored by the Semiconductor Research Corporation (SRC) and the Future and Emerging Technologies (FET) programme within the Seventh Framework Program for Research of the European Commission (FET-Open grant number 270749, ‘2D-Nanolattices’ project). D.A. acknowledges the TI/Jack Kilby Faculty Fellowship. The authors thank A. Nayak and J. Wozniak of Texas Advanced Computing Centre (TACC) for their help with the three-dimensional rendering of Figure 1.

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E.C., D.C. and C.G. performed epitaxial growth of silicene with in situ RHEED and STM characterization. L.T. and E.C. conducted Raman spectroscopy studies on silicene stability. L.T., with D.A., devised and conducted the silicene transfer, device fabrication, transport measurements and analysis of device data. M.F. and A.M. managed the technical resources at the Laboratorio MDM, National Research Council (CNR) – Institute for Microelectronics and Microsystems (IMM), Italy. All authors contributed to the writing based on the draft written by L.T. and D.A. D.A. and A.M. coordinated and supervised the research.

Corresponding authors

Correspondence to Alessandro Molle or Deji Akinwande.

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The authors declare no competing financial interests.

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Tao, L., Cinquanta, E., Chiappe, D. et al. Silicene field-effect transistors operating at room temperature. Nature Nanotech 10, 227–231 (2015). https://doi.org/10.1038/nnano.2014.325

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