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Sketched oxide single-electron transistor

Nature Nanotechnology volume 6, pages 343–347 (2011)Cite this article

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Abstract

Devices that confine and process single electrons represent an important scaling limit of electronics1,2. Such devices have been realized in a variety of materials and exhibit remarkable electronic, optical and spintronic properties3,4,5. Here, we use an atomic force microscope tip to reversibly ‘sketch’ single-electron transistors by controlling a metal–insulator transition at the interface of two oxides6,7,8. In these devices, single electrons tunnel resonantly between source and drain electrodes through a conducting oxide island with a diameter of ∼1.5 nm. We demonstrate control over the number of electrons on the island using bottom- and side-gate electrodes, and observe hysteresis in electron occupation that is attributed to ferroelectricity within the oxide heterostructure. These single-electron devices may find use as ultradense non-volatile memories, nanoscale hybrid piezoelectric and charge sensors, as well as building blocks in quantum information processing and simulation platforms.

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Figure 1: SketchSET schematic and transport characteristics.
Figure 2: Temperature-dependent differential conductance and capacitance of device A.
Figure 3: Device B side gating at T = 25 K.
Figure 4: Differential conductance and capacitance dependence on back-gate voltage at T = 16 K, device C.

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Acknowledgements

This work was supported by US National Science Foundation (DMR-0704022 and DMR-0906443), US Defense Advanced Research Projects Agency (W911NF-09-10258), US Army Research Office (W911NF-08-1-0317), The Fine Foundation, US Air Force Office of Scientific Research (FA9550-10-1-0524), a David and Lucile Packard Fellowship and the Fundação de Amparo à Pesquisa do Estado de São Paulo – FAPESP (contact project 05/04643-7).

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Authors and Affiliations

  1. Department of Physics and Astronomy, University of Pittsburgh, Pittsburgh, 15260, Pennsylvania, USA

    Guanglei Cheng, Feng Bi, Cheng Cen, Daniela F. Bogorin & Jeremy Levy

  2. Laboratório Nacional de Luz Síncrotron, Caixa Postal 6192, Campinas, 13083-970, SP, Brazil

    Pablo F. Siles

  3. Instituto de Física ‘Gleb Wataghin’, Universidade Estadual de Campinas-UNICAMP, Campinas, SP, Brazil

    Pablo F. Siles

  4. Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin, 53706, USA

    Chung Wung Bark, Chad M. Folkman, Jae-Wan Park & Chang-Beom Eom

  5. Hewlett Packard Laboratories, 1501 Page Mill Road, Palo Alto, 94304, California, USA

    Gilberto Medeiros-Ribeiro

Authors
  1. Guanglei Cheng
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Contributions

G.C. carried out the major experiments. P.F.S. and C.C. carried out preliminary experiments. F.B., G.C. and D.F.B. contributed to device fabrication. C.W.B., C.M.F., J.W.P. and C.B.E. contributed to sample growth. J.L., G.C., C.C. and G.M.R. discussed and analysed the results. All authors contributed to writing of the manuscript.

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Correspondence to Jeremy Levy.

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The authors declare no competing financial interests.

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Cheng, G., Siles, P., Bi, F. et al. Sketched oxide single-electron transistor. Nature Nanotech 6, 343–347 (2011). https://doi.org/10.1038/nnano.2011.56

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