The basic active devices of almost all the flat-panel displays currently available are amorphous- or poly-silicon-based thin-film transistors (TFTs). Such TFTs are also expected to be used in the development of the drivers and logic circuits of future devices, including low-cost, printable and flexible e-papers and radio-frequency identification tags. For such applications, it is advantageous that the semiconductor material for the active layer be deposited on a plastic substrate using a fast, low-temperature and non-vacuum process. Here, we present such a technique, realizing high-performance TFTs and integrated circuits based on random carbon nanotube networks.

Figure 1a shows the basic concept of the device fabrication process. Carbon nanotubes are continuously grown using an atmospheric-pressure floating-catalyst (aerosol) chemical vapour deposition (FC-CVD) technique by feeding a carbon source gas with a catalyst precursor12. The nanotubes are then collected on a membrane filter, at room temperature, for a short time, usually between 1 and 5 s. By dissolving the filter in acetone, the as-grown nanotubes are transferred from the filter to the substrate on which the TFT electrodes have been prepared. The fabrication procedure is completed by removing the nanotubes located outside the channel areas using oxygen plasma treatment, so that each device is electrically separated (see Methods for details).

Figure 1: Carbon nanotube growth and device fabrication.
figure 1

a, Schematic of carbon nanotube growth, collection by filter, transfer and patterning. b, SEM image of carbon nanotube film transferred onto a Si/SiO2 substrate. Carbon nanotube collection time, 2 s. Inset: magnified view of Y-junctions. The red and blue arrows indicate X- and Y-junctions, respectively. c, Schematics of X- and Y-junctions. d, Transfer (ID − VGS) characteristics at various VDS values ranging from −0.5 to −5 V. Lch = Wch = 100 µm. Inset: schematics of the bottom-gate carbon nanotube TFT on a Si/SiO2 substrate. e, Output (ID − VDS) characteristics of the same device exhibiting saturation behaviour.

The transferred carbon nanotube film has a network morphology consisting of rather straight and long nanotubes, ~10 µm in length, as shown in the scanning electron microscopy (SEM) images in Fig. 1b, and the carbon nanotube network consists mainly of individual nanotubes (Supplementary Section 1). The morphology of this film is quite unique when compared to those comprising nanotubes prepared by solution-based techniques4,10,13,14 and by direct deposition onto a substrate through FC-CVD (Supplementary Section 2). A number of the junctions occurring between nanotubes are Y-type rather than X-type. Because there is strong coupling of carrier wavefunctions at nanotube–nanotube contacts that have a large area, the Y-junctions (which have a large junction area) can have lower junction resistances than the X-junctions (which have a small junction area and therefore a high contact resistance) (Fig. 1c). Indeed, others have recently shown experimentally that the inter-nanotube resistance of Y-junctions is lower than that of X-junctions15. Given that the Y-junctions in our study were also observed in the carbon nanotube network on the membrane filter (Supplementary Section 3), they could have been formed by van der Waals interactions among nanotubes downflow of an aerosol containing nanotubes in the reactor.

Figure 1d,e presents the transfer and output characteristics of a carbon nanotube TFT device with an optimized density of nanotubes (collection time of 2 s). This device was fabricated on a heavily doped p-Si substrate with a 100-nm-thick SiO2 layer. The substrate was used as the back gate, and the channel length (Lch) and channel width (Wch) were both 100 µm. The device showed p-type characteristics with a high on/off ratio of 6 × 106 and an effective device mobility of 35 cm2 V−1 s−1, which was evaluated by the standard formula μ = (Lch/Wch)(1/C)(1/VDS)(dID/dVGS), where C is the gate capacitance. We calculated C using a parallel plate model as ɛ/tox, where tox and ɛ are the thickness and dielectric constant, respectively, of the gate insulator. This model is commonly used to evaluate mobility as a performance index of common TFTs such as silicon, organic and other semiconductors TFTs with a sheet channel. In the case of carbon nanotube TFTs, however, the parallel plate model overestimates the gate capacitance when the density of nanotubes is low, as in the present case. A more rigorous model that takes into account the realistic electrostatic coupling between sparse nanotubes and the gate electrode is therefore often used to estimate the gate capacitance of carbon nanotube TFTs2,16. The mobility of our fabricated TFT as evaluated by the rigorous model was 634 cm2 V−1 s−1 (Supplementary Section 4). Previous studies3,17,18 have reported that the on/off ratio of TFTs degrades considerably with increasing VDS. However, the present device maintained an on/off ratio as high as 1 × 106 at a VDS of −5 V. Details on the degradation of the on/off ratio are provided in Supplementary Section 5.

Generally, the mobility of carbon nanotube TFTs as evaluated by the parallel plate model increases with increasing density (ρCNT) and length (LCNT) of the nanotubes. However, when LCNT is comparable to Lch, or when ρCNT of the metallic nanotubes exceeds the percolation threshold19 ρth = 4.242LCNT2, the metallic nanotubes can connect the source and drain directly, resulting in a drastic increase in the off-current. Thus, there is a trade-off between mobility and the on/off ratio. Figure 2 shows the mobility and the on/off ratio of 36 carbon nanotube TFTs (Lch = 100 µm) fabricated by our group, together with those of other TFTs based on carbon nanotubes3,5,10,13,14,17,18,20,21,22, amorphous silicon, polycrystalline silicon23, ZnO2 and related materials24, and organic semiconductors25,26,27. These mobilities were evaluated using the parallel plate model for comparison purposes. The typical mobility and on/off ratio of our fabricated TFTs are ~20 cm2 V−1 s−1 and ~1 × 106, and the corresponding maximum values are 68.3 cm2 V−1 s−1 (with an on/off ratio of 1.5 × 104) and 1.6 × 107 (with a mobility of 7.3 cm2 V−1 s−1), respectively. Comparisons of the present TFTs with those in recent representative reports, including TFTs with semiconductor-enriched nanotubes10,14,18, reveal that the former have significantly better performance. Our TFTs are also comparable in performance to low-temperature poly-Si (LTPS)23 and InGaZnO TFTs24, which require conventional vacuum processes for deposition on a substrate.

Figure 2: Mobility and on/off ratio.
figure 2

Comparison of 36 carbon nanotube TFTs with Lch = 100 µm and other representative TFTs based on carbon nanotube networks, amorphous silicon, polycrystalline silicon, ZnO-based semiconductors, and organic materials. Given that different methods were used for calculating the mobility of the carbon nanotube TFTs, the mobilities in refs 3 and 13 were re-evaluated.

Although our devices consist of as-grown carbon nanotubes, of which ~30% are metallic nanotubes (Supplementary Section 6), they simultaneously showed both a high mobility and a high on/off ratio. The high mobility originates from the unique morphology of the nanotube film, that is, the network of long nanotubes connected by Y-junctions, with their reduced inter-nanotube junction resistances, and the number of junctions along the current flow paths. The high on/off ratio is attributed to the reduction in the density of metallic nanotubes below ρth by the precise control of ρCNT; such precise control can be achieved in FC-CVD by adjusting the collection time (Supplementary Section 7). Figure 3 presents statistical data regarding the on/off ratio. Figure 3a shows the Lch dependence of the on-current (Ion), off-current (Ioff) and on/off ratio. Although Ion exhibits an almost inversely proportional dependence on Lch, Ioff falls in the range of Lch values from 20 to 50 µm; accordingly, a high on/off ratio is obtained for Lch values longer than 40 µm. The behaviour of Ioff can be divided into three regions (I − III in Fig. 3a). In region I, that is, when Lch is comparable to LCNT, metallic nanotubes may directly bridge the source and drain electrodes. When Lch > LCNT (region II), conduction in the nanotube network is described by percolation theory as being that of a non-classical two-dimensional conductor. The current is expressed as I (LCNT/Lch)m/LCNT, where the exponent m is a universal constant that depends on the normalized nanotube coverage19, ρCNTLCNT2. In region II, the m value for Ioff is as high as ~14, indicating that a nearly ideal condition, that is, ρCNT of metallic nanotubes < ρth, has been reached. A detailed analysis of the m value for various ρCNT values, based on a previous report by Kocabas and colleagues19, is presented in Supplementary Section 8. In region III, Ioff is generated by thermally excited carriers at room temperature.

Figure 3: Channel-length dependence and statistics of on/off ratio.
figure 3

a, Plot of on-current, off-current and on/off ratio versus channel length at VDS = −0.5 V. VGS is swept from −10 to 10 V. Twenty TFTs are measured for each Lch. In the lower panel, solid circles and squares represent the median, and the upper and lower bands of the boxes correspond to the 75th and 25th percentiles, respectively, of the device population. In region I, metallic nanotubes may directly bridge the source and drain electrodes. Region II is described by percolation theory. In region III, Ioff is generated by thermally excited carriers. b, Histograms of the distribution of the on/off ratio for Lch values ranging from 5 to 100 µm. Forty-six TFTs were considered for each value of Lch in the statistical analysis. Red curves are Gaussian fits. Blue and green lines indicate the separate groups of devices with and without metallic paths, respectively.

Figure 3b shows the distribution of the on/off ratios of 320 TFTs with a collection time of 2 s, over an Lch range of 5–100 µm. For Lch = 100 µm, 91% (77%) of the TFTs have on/off ratios higher than 1 × 105 (1 × 106); the median value in this case is 4 × 106. The bimodal distribution of the on/off ratio, which can be seen for Lch from 30 to 50 µm, indicates the presence of separate groups of devices with and without metallic paths (indicated by blue and green lines, respectively). Such a mode transition occurs at values of Lch several times longer than LCNT, namely, in region II.

The gas-phase filtration and transfer process used in this study to fabricate carbon nanotube thin films can be applied to device fabrication on flexible plastic substrates. Here, we demonstrate carbon nanotube TFTs and integrated circuits, including inverters, ring oscillators (3, 11 and 21 stages), NOR and NAND gates, reset–set flip-flops, and delay flip-flops on a polyethylene naphthalate (PEN) substrate (Fig. 4a). Figure 4b shows a schematic cross-section of a bottom-gate carbon nanotube TFT on a PEN substrate. Lch and Wch of the TFTs in the circuits were designed to be 100 µm each. The performance of the TFTs on the PEN substrate was found to be similar to that of TFTs on a silicon substrate (Fig. 4c). Figure 4d shows the input–output characteristics of an inverter. Here, the load is a gate-source-shorted carbon nanotube TFT, which is lightly doped with F4TCNQ (tetrafluorotetracyano-p-quinodimethane) to adjust the logic threshold voltage28. The inverter exhibits excellent transfer characteristics with a maximum voltage gain of 16 at a supply voltage (VDD) of −5 V. The large area of the eye pattern in the folded transfer curve implies a large noise margin for logic operation and allows us to construct logic integrated circuits. The noise margin, in fact, decreases because of the hysteresis of the present TFTs. Further details on the hysteresis of a TFT and its effect on the noise margin of an inverter are given in Supplementary Section 9.

Figure 4: Carbon nanotube TFTs and integrated circuits on a flexible substrate.
figure 4

a, Photograph of devices fabricated on a flexible and transparent PEN substrate. b, Schematic cross-section of a bottom-gate TFT on a PEN substrate with an Al2O3 gate insulator. c, Transfer characteristics of a typical TFT with Lch = 100 µm at VDS = −0.5 V, Wch = 100 µm. d, Input–output and gain characteristics of an inverter. Insets: optical micrograph, circuit diagram and symbol of the inverter. e,f, Optical micrograph and circuit diagram of a 21-stage ring oscillator. g, Output characteristics of the ring oscillator with an oscillation frequency of 2.0 kHz at VDD = −4 V.

Figure 4e−g shows diagrams and graphs for a 21-stage ring oscillator with an output buffer on a PEN substrate, into which 44 carbon nanotube TFTs are integrated. The output voltage begins oscillating spontaneously at VDD ≈ −2 V, and the oscillation frequency reaches 2.0 kHz at a VDD of −4 V (Fig. 4g). This circuit demonstrates the good uniformity characteristic of the present TFTs. The delay time of each inverter, 1/2Nf, where N and f are the number of stages and the oscillation frequency, respectively, is 12 µs. This value is significantly better than that reported in a recent study17.

Figure 5 presents basic logic gates (NOR and NAND) and an integrated circuit (master–slave delay flip-flops) fabricated on the PEN substrate. (For the case of reset–set flip-flops, see Supplementary Section 10.) NOR (Fig. 5a−d) and NAND (Fig. 5e−h) gates operated by a clock (CLK) signal at 100 Hz show clear logic outputs with the large voltage swings, which contribute to the robust operation of the integrated circuits. The delay flip-flop, which is capable of serving as a delay or one memory bit because of its two stable states, is currently the most commonly used flip-flop. Figure 5i−m shows a master–slave delay flip-flop consisting of eight NAND and two NOT gates on a PEN substrate. The circuit consists of two gated delay latches connected in series, where the slave latch changes the state in response to a change in the state of the master latch. The input–output characteristics (Fig. 5m) show that the master–slave delay flip-flop is triggered on the rising edge of the CLK signal. The output Q state changes in accordance with the input DATA only when the CLK signal becomes HIGH (−5 V). Thus, latching behaviour is confirmed.

Figure 5: Logic gates and delay flip-flops on a flexible substrate.
figure 5

ad, NOR gate. eh, NAND gate. im, Master–slave delay flip-flop. Each panel includes an optical micrograph, circuit symbol, truth table and input–output characteristics of the device. In l, ‘X’ denotes a ‘don't care’ condition and ‘*’ denotes ‘no change’ in output. The master–slave delay flip-flop is triggered on the rising edge of the CLK signal.

Two types of logic circuits exist in digital circuit theory: combinational logic and sequential logic. In the case of combinational logic circuits, the output is a function only of the present input. In contrast, the output of sequential logic circuits depends on not only the present input but also the history of the input. In other words, sequential logic has storage or memory functions. The master–slave delay flip-flop we have presented here is the first sequential logic circuit based on carbon nanotube transistors.

Finally, we comment on the potential applicability of our carbon nanotube TFTs to large-scale flexible electronics. The atmospheric-pressure gas-phase nanotube filtration and transfer process used in this study can yield carbon nanotube films with good uniformity over a large area (Supplementary Section 11). The filtration process can be scaled up easily by increasing the widths of the nozzle and filters and by using the roll-to-roll method for the filter. The lithographic techniques used in this study for carbon nanotube patterning and the fabrication of electrodes and wire connections will possibly be replaced with printing techniques such as screen and gravure printing with high throughput. A combination of these techniques should pave the way to our ambitious goal: developing large-scale, low-cost and flexible electronics.


Synthesis of carbon nanotubes

Carbon nanotubes were grown using a floating-catalyst (aerosol) CVD technique with carbon monoxide (CO) as the carbon source, and catalyst particles were produced by decomposition of ferrocene vapour (FeCp2, 99%, Strem Chemicals). CO (standard 300 cm3 min−1) was passed through a cartridge containing ferrocene powder mixed with silicon dioxide powder (99.9%, Balzers Materials, weight ratio FeCp2:SiO2 = 1:4), maintaining conditions for ferrocene vapour saturation (0.7 Pa at room temperature). Additional CO (standard 100 cm3 min−1) was introduced into the furnace. Growth temperature was set to 880 °C. The growth procedure is described elsewhere in greater detail12. The carbon nanotube network was collected by filtering through membrane filters (Millipore) of cellulose acetate mixed with nitrocellulose at room temperature.

Carbon nanotube network transfer process

The carbon nanotube network was transferred from a membrane filter to the substrate by dissolving the filter in acetone. A membrane filter with a carbon nanotube network was placed on the substrate so that the side with the nanotube network contacted the top surface of the substrate. Several droplets of isopropyl alcohol (IPA) were dropped by a pipette onto the filter to attach the filter to the substrate by surface tension. The resultant filter-attached substrate was soaked in an acetone bath to completely dissolve the filter.

Fabrication of TFTs and integrated circuits

Bottom-gate TFTs were fabricated on a highly doped p-Si substrate with a thermally grown SiO2 layer (100 nm) as a gate dielectric. The bottom-gate electrode (Ti/Au: 10/100 nm) was deposited by electron-beam evaporation after the SiO2 layer on the back-side of the wafer was etched by reactive ion etching (RIE). Source and drain electrodes (Ti/Au: 10/100 nm) were fabricated by standard photolithography, electron-beam evaporation and lift-off processes. Subsequently, the carbon nanotube network was transferred from the membrane filter to the substrate with patterned electrodes. Carbon nanotubes outside the channel area were removed by oxygen plasma.

In the case of PEN substrates (Teijin DuPont Films; thickness, 125 µm), the process temperature was controlled to below 145 °C throughout device fabrication. After formation of gate electrodes, a 40 nm Al2O3 insulator layer was deposited on the substrate by an atomic layer deposition technique using trimethylaluminium (TMA) and H2O at 145 °C. Contact windows for the gate electrodes were then opened by photolithography and RIE. Similar processes to those described above for the silicon substrate were adopted for the fabrication of source and drain electrodes as well as transfer and patterning of the carbon nanotube network on the PEN substrate.