A CMOS-capable silicon nanowire transistor has been fabricated without any junctions, simplifying its manufacture and improving its performance relative to traditional devices.
This is a preview of subscription content, access via your institution
Access options
Subscribe to this journal
Receive 12 print issues and online access
$259.00 per year
only $21.58 per issue
Buy this article
- Purchase on Springer Link
- Instant access to full article PDF
Prices may be subject to local taxes which are calculated during checkout
References
Lilienfeld, J. E. Method and apparatus for controlling electric current. US patent 1,745,175 (1925).
Shan, Y., Ashok, S. & Fonash, S. J. Appl. Phys. Lett. 91, 093518 (2007).
Lin, Y.-W., Marek-Sadowska, M., Maly, W., Pfitzner, A. & Kasprowicz, D. in Int. Conf. Computer Design 557–562 (IEEE, 2008).
Soree, B. & Magnus, W. in 10th Int. Conf. Ultimate Integration of Silicon 245–248 (IEEE, 2009).
Lee, C. W. et al. Appl. Phys. Lett. 94, 053511 (2009).
Colinge, J. P. et al. Nature Nanotech. 5, 225–229 (2010).
Tsutsui, K. et al. in Int. Workshop Nano CMOS 56–68 (IEEE, 2006).
Aoyama, T. et al. in Int. Workshop Junction Technol. 110–115 (IEEE, 2009).
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Ionescu, A. Nanowire transistors made easy. Nature Nanotech 5, 178–179 (2010). https://doi.org/10.1038/nnano.2010.38
Issue Date:
DOI: https://doi.org/10.1038/nnano.2010.38
This article is cited by
-
High-K Spacer Dual-Metal Gate Stack Underlap Junctionless Gate All Around (HK-DMGS-JGAA) MOSFET for high frequency applications
Microsystem Technologies (2020)
-
Threshold voltage modeling for a Gaussian-doped junctionless FinFET
Journal of Computational Electronics (2019)
-
Design and structural optimization of junctionless FinFET with Gaussian-doped channel
Journal of Computational Electronics (2018)
