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Nanowire transistors without junctions


All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult fabrication challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

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Figure 1: Schematic of an n-channel nanowire transistor.
Figure 2: Transmission electron micrograph of silicon gated resistor nanoribbons.
Figure 3: Current–voltage characteristics.
Figure 4: Measured output characteristics of gated resistors.
Figure 5: Electron concentration contour plots in an n-type junctionless gated resistor.
Figure 6: Intrinsic device delay time for a MOSFET and for gated resistors.


  1. Lilienfeld, J. E. Method and apparatus for controlling electric current. US patent 1,745,175 (1925).

  2. Lilienfeld, J. E. Device for controlling electric current. US patent 1,900,018 (1928).

  3. Weis, M. et al. Low power SRAM cell using vertical slit field effect transistor (VeSFET). ESSCIRC Fringe P6 (2008).

  4. Sorée, B., Magnus, W. & Pourtois, G. Analytical and self-consistent quantum mechanical model for a surrounding gate MOS nanowire operated in JFET mode. J. Comput. Electron. 7, 380–383 (2008).

    Article  Google Scholar 

  5. Sorée, B. & Magnus, W. Silicon nanowire pinch-off FET: basic operation and analytical model. Ultimate Integration on Silicon Conference (ULIS) 18–20 Poster 249 (2009).

    Google Scholar 

  6. Lee, C. W. et al. Junctionless multigate field-effect transistor. Appl. Phys. Lett. 94, 053511 (2009).

    Article  Google Scholar 

  7. Cui, Y., Zhong, Z., Wang, D., Wang, W. U. & Lieber, C. M. High performance silicon nanowire field effect transistors. Nano Lett. 3, 149–152 (2003).

    Article  CAS  Google Scholar 

  8. Shan, Y., Ashok, S. & Fonash, S. J. Unipolar accumulation-type transistor configuration implemented using Si nanowires. Appl. Phys. Lett. 91, 093518 (2007).

    Article  Google Scholar 

  9. Lu, W., Xie, P. & Lieber, C. M. Nanowire transistor performance limits and applications. IEEE Trans. Electron Dev. 55, 2859–2876 (2008).

    Article  CAS  Google Scholar 

  10. Xiang, J., Lu, W., Wu, Y., Yan, H. & Lieber, C. M. Ge/Si nanowire heterostructures as high-performance field-effect transistors. Nature 441, 489–493 (2006).

    Article  CAS  Google Scholar 

  11. Doyle, B. S. et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron. Dev. Lett. 24, 263–265 (2003).

    Article  CAS  Google Scholar 

  12. Colinge, J. P. FinFETs and Other Multi-Gate Transistors (Springer, 2007).

    Google Scholar 

  13. Colinge, J. P. et al. Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs. Microelectron. Eng. 86, 2067–2071 (2009).

    Article  Google Scholar 

  14. Afzalian, A. et al. MultiGate SOI MOSFETs: accumulation-mode vs. enhancement-mode. IEEE 2008 Silicon Nanoelectronics Workshop P1–6 (2008).

  15. Jacoboni, C., Canali, C., Ottaviani, G. & Quaranta, A. A. A review of some charge transport properties of silicon. Solid-State Electron. 20, 77–89 (1977).

    Article  Google Scholar 

  16. Thompson, S. E. et al. A 90-nm logic technology featuring strained-silicon. IEEE Trans. Electron. Dev. 51, 1790–1797 (2004).

    Article  CAS  Google Scholar 

  17. Ramos, J. et al. Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs. International Conference on Solid-State and Integrated Circuit Technology 72–74 (2006).

  18. Weber, O. et al. High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding. Tech. Dig. IEDM 245–248 (2008).

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This work is supported by the Science Foundation Ireland grant 05/IN/I888: ‘Advanced scalable silicon-on-insulator devices for beyond-end-of-roadmap semiconductors’. This work has also been made possible by the Programme for Research in Third-Level Institutions. This work was supported in part by the European Community (EC) Seventh Framework Program through the Networks of Excellence NANOSIL and EUROSOI+ under contracts 216171 and 216373. The authors wish to thank R. Nagle, R. Dunne and S. Cosgrove for TEM analysis.

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I.F., B.O'N., A.B., M.W., A.M.K. and B.McC. were responsible for device processing and I.F. and R.M. for device layout. A.A., N.D.A., R.Y., C.W.L. and P.R. performed device simulations. C.W.L. performed the electrical measurements and J.P.C. designed the devices and wrote the paper. All authors discussed the results and commented on the manuscript.

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Correspondence to Jean-Pierre Colinge.

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Colinge, JP., Lee, CW., Afzalian, A. et al. Nanowire transistors without junctions. Nature Nanotech 5, 225–229 (2010).

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