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Nanoscale memory cell based on a nanoelectromechanical switched capacitor

Nature Nanotechnology volume 3, pages 26–30 (2008)Cite this article

Abstract

The demand for increased information storage densities has pushed silicon technology to its limits and led to a focus on research on novel materials and device structures, such as magnetoresistive random access memory1,2,3 and carbon nanotube field-effect transistors4,5,6,7,8,9, for ultra-large-scale integrated memory10. Electromechanical devices are suitable for memory applications because of their excellent ‘ON–OFF’ ratios and fast switching characteristics, but they involve larger cells and more complex fabrication processes than silicon-based arrangements11,12,13. Nanoelectromechanical devices based on carbon nanotubes have been reported previously14,15,16,17, but it is still not possible to control the number and spatial location of nanotubes over large areas with the precision needed for the production of integrated circuits. Here we report a novel nanoelectromechanical switched capacitor structure based on vertically aligned multiwalled carbon nanotubes in which the mechanical movement of a nanotube relative to a carbon nanotube based capacitor defines ‘ON’ and ‘OFF’ states. The carbon nanotubes are grown with controlled dimensions at pre-defined locations on a silicon substrate in a process that could be made compatible with existing silicon technology, and the vertical orientation allows for a significant decrease in cell area over conventional devices. We have written data to the structure and it should be possible to read data with standard dynamic random access memory sensing circuitry. Simulations suggest that the use of high-k dielectrics in the capacitors will increase the capacitance to the levels needed for dynamic random access memory applications.

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Figure 1: A NEM switch based on vertically aligned multiwalled carbon nanotubes.
Figure 2: NEM switching characteristics.
Figure 3: The capacitance of a NEM switch.
Figure 4: Writing and reading data to a NEM memory cell.

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Authors and Affiliations

  1. Electrical Engineering Division, Department of Engineering, University of Cambridge, 9 JJ Thomson Avenue, Cambridge, CB3 0FA, UK

    Jae Eun Jang, Seung Nam Cha, Young Jin Choi, Tim P. Butler & Gehan A. J. Amaratunga

  2. Samsung Advanced Institute of Technology, Yongin, 449-712, Korea

    Jae Eun Jang, Seung Nam Cha, Jae Eun Jung & Jong Min Kim

  3. BK 21 Physics Research Division, Center for Nanotubes and Nanostructured Composites, SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon, 440-746, Korea

    Dae Joon Kang

  4. Microelectronics Research Centre, Cavendish Laboratory, University of Cambridge, Cambridge, CB3 0HE, UK

    David G. Hasko

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  1. Jae Eun Jang
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  4. Dae Joon Kang
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  8. Jong Min Kim
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Contributions

J.E.J. was involved in project conception, planning, experimental work and data analysis, S.N.C. in project conception, experimental work and data analysis, Y.J.C., T.B., D.J.K. and J.E. Jung in experimental work, D.G.H. in experimental guidance and direction, J.M.K. in project conception and data analysis, G.A.J.A. in project conception and guidance, data analysis and interpretation.

Correspondence and requests for materials should be addressed to G.A.J.A.

Corresponding author

Correspondence to Gehan A. J. Amaratunga.

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Jang, J., Cha, S., Choi, Y. et al. Nanoscale memory cell based on a nanoelectromechanical switched capacitor. Nature Nanotech 3, 26–30 (2008). https://doi.org/10.1038/nnano.2007.417

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