Inside the 'dead layer'

Simulations explain why nanocapacitors do not work as well as expected

The ‘dead layer’ that reduces the capacitance of nanoscale capacitors is a fundamental property of these devices and is not due to defects and strains introduced during processing. Massimiliano Stengel and Nicola Spaldin of the University of California, Santa Barbara, have reached this conclusion following a series of ab initio calculations of the dielectric properties of nanocapacitors made of different materials¹.

Capacitors are often the largest components in integrated circuits, which is why there is widespread interest in reducing their size. A capacitor consists of an insulating material sandwiched between two metal plates, and research has focused on the use of insulators with a high permittivity, such as SrTiO₃. However, experiments on thin-film devices have found that the capacitance of SrTiO₃ devices are orders of magnitude less than expected, and it has been widely assumed that this poor performance was due to the presence of a dead layer. The simulations by Stengel and Spaldin confirm that this layer is a basic property of the interface, and not the result of processing, although defects and strains introduced during processing will cause further deterioration in performance.

Stengel and Spaldin have modelled capacitors made of SrTiO₃ between three electrodes and conclude that metals with short electronic screening lengths — such as gold and platinum — lead to the best performance.