Growing along

Appl. Phys. Lett. 99, 203104 (2011)

Common growth methods for semiconductor nanowires usually yield vertical structures. To incorporate such vertical nanowires in planar electronic devices requires them to be transferred from the growth support to a flat substrate, followed by a complex alignment and lithography process. Building on previous work, Linwei Yu and colleagues have now fabricated coplanar silicon nanowire transistors in a self-aligned growth process. The researchers first pattern silicon nitride (SiN) slabs on top of a silicon substrate with a silicon dioxide layer, which later serves as a bottom gate. They then form indium droplets near the SiN slabs and coat the entire structure with a thin layer of amorphous silicon. During the temperature-driven solid–liquid–solid growth process, the indium droplets serve as mobile catalytic particles, consuming the amorphous silicon to leave behind silicon nanowires as they move along the edges of the SiN structures. Using their method, the researchers have fabricated nanowires with diameters down to 14 nm and field-effect transistors with hole mobilities of up to 228 cm² Vs⁻¹, which are comparable to devices based on polycrystalline silicon.