Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (‘sub-kT/q’) and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor’s source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.
Metal-oxide-semiconductor field-effect transistors (MOSFETs) have been the workhorse of digital computation. In a conventional MOSFET (Fig. 1a), a change in the drain-to-source current (IDS) can be induced by the application of a transverse electric field across the gate dielectric by means of the third gate terminal. This field lowers the potential energy barrier separating the source and the channel, exponentially increasing the number of carriers traversing the channel. At room temperature, a minimum change of 60 mV in the gate bias (VGS) is required to effectuate a decade change in IDS, setting up the so-called ‘60 mV per decade’ limit, also known as the ‘Boltzmann limit’ (Fig. 1a). Stemming from the statistical distribution of free and independent carriers in conventional semiconductors and determined by the thermal voltage kT/q (k: Boltzmann constant; T: temperature; q: electron charge), this fundamental limit restricts transistor performance, particularly at low-operating voltages1,2,3,4, and has motivated the exploration of FETs that harness collective carrier responses5,6,7,8,9,10,11,12,13. Such collective behaviour—wherein a small external perturbation can trigger an aggregated change in the ground state of the system—can produce internal amplification; and provide a pathway to overcome the Boltzmann limit to enable FET’s with sub-kT/q (kT/ηq; η>1) switching slope and superior performance at low voltages. Particularly, in insulator-to-metal transition (IMT) materials14 that exhibit strong correlation, like VO2 (refs 15, 16, 17, 18), the collective response to external perturbation (temperature19,20, pressure21,22 and electrical stimulus23,24,25,26,27,28) can be the ‘melting’ of carriers, marking an electronic phase transformation where the electrons localized at atomic sites change to an itinerant state (Fig. 1b). This phase transformation amplifies the free-carrier concentration29; and in the case of VO2, manifests itself as a sharp change in resistivity up to five orders in magnitude30 at ∼340 K. However, attempts to realize IMT-based three-terminal transistor devices with a solid-state gate dielectric to induce the phase transition directly in the channel material have experienced only limited success23,31,32,33. Further, the alternate approach of using an ionic liquid as the gate dielectric, which is the focus of current research34,35,36,37,38,39, is typically slow40,41,42 and susceptible to electrochemical effects43. These constraints have restricted the utilization of this collective phenomenon in FETs for advanced high-performance electronic applications.
Here, we explore a novel transistor architecture that harnesses the abrupt free-carrier amplification across the phase transition in VO2 using a conventional MOSFET. By electrically coupling the VO2 in series with the source of a conventional MOSFET (Fig. 1b), we design a hybrid-phase-transition-FET (hyper-FET) wherein, for a given drain-to-source voltage (VDS), the gate bias VGS modifies the current IDS flowing through the MOSFET channel and the VO2 in series, triggering an abrupt phase transformation in VO2. The proposed hyper-FET not only exhibits steep-slope characteristics but also circumvents the need for a direct field-induced phase transition in VO2 with a solid-state gate dielectric. Further, the abrupt resistivity switching of VO2 in the hyper-FET configuration, which is the origin of the steep-slope characteristics, induces a negative differential resistance (NDR) across VO2 that results in internal voltage amplification which consequently enhances the hyper-FET’s performance beyond that of a conventional MOSFET.
Experimental demonstration and operation principle
Figure 2a illustrates the schematic of an experimental hyper-FET consisting of a two-terminal VO2 device in series with the channel of a conventional Si n-MOSFET (individual device characteristics are shown in Supplementary Fig. 1 and discussed in Supplementary Note 1). All measurements in this work are performed at room temperature (T=300 K). The modulation in the transfer characteristics (IDS–VGS) of the hyper-FET is shown in Fig. 2b. Initially, at VGS=0 V (MOSFET in OFF-state), VO2 is in the high-resistivity insulating state. In this series combination, VDS is divided between the MOSFET channel and the insulating VO2 in proportion to their respective resistances; and the current IDS through the channel and VO2 is insufficient to induce an IMT. As VGS increases, the MOSFET-channel resistance decreases until IDS reaches a critical current threshold, IIMT. This triggers an abrupt IMT with the VO2 transforming into the low-resistivity metallic state that consequently leads to an abrupt increase in IDS (turn-ON). Similarly, as VGS reduces, the MOSFET-channel resistance increases until IDS drops to a critical threshold value, IMIT, and the VO2 transforms back to the high-resistivity insulating state accompanied by an abrupt reduction in IDS (turn-OFF). The difference between the critical threshold values (IMIT>IIMT; corresponding to VGS,IMT, VGS,MIT, respectively) results in hysteresis (=VGS,IMT−VGS,MIT) (Fig. 2b).
Analysing the switching slope , shown in Fig. 2c, it is evident that the abrupt change in current associated with the IMT/MIT in VO2 results in steep-slope (S<60 mV per decade) characteristics, both during the forward and the reverse VGS sweep. We emphasize that the current change ΔIDS is abrupt and the extracted value of S is limited by the voltage resolution (1 mV). The corresponding output characteristics (IDS–VDS) of the hyper-FET (Fig. 2d) show excellent IDS saturation behaviour, which is paramount for small signal amplification. This is in contrast to the traditional IMT-based transistor design where the IMT occurs in the channel material23. Such a transistor is unlikely to demonstrate current saturation since the design envisages the IMT channel to have a metallic character in the transistor’s ON-state which fundamentally cannot sustain a drain side depletion region.
Internal amplification in the hyper-FET
To elucidate the internal amplification, we analyze the current–voltage dynamics across VO2 in the hyper-FET configuration (Fig. 2e). In this series combination, the abrupt IMT results in an NDR across the VO2. Such an NDR is induced because when the VO2 resistance decreases abruptly, it results in (a) an increase in IDS (ΔIDS) which flows through the VO2 device and the MOSFET channel in series; (b) a reduction in the voltage across the VO2 device (−ΔVNDR) (see Supplementary Fig. 2 and Supplementary Note 2 for discussion on the NDR in VO2). The effective gate-to-source voltage across the MOSFET (VGS′; S′: internal node in Fig. 2a) when VO2 is in the insulating state (hyper-FET OFF-state) is VGS′=VGS−. It can be observed that the voltage across the insulating VO2 results in an additional voltage drop (=−) in the effective gate-to-source voltage VGS′. Across the IMT in VO2 which induces the NDR, this voltage drop (=−) reduces by ΔVNDR (therefore increasing VGS′ by ΔVNDR; Fig. 2a). Thus, the additional voltage drop (=−) in VGS′ when VO2 is in the insulating state results in a drastic reduction in the OFF-state current (IDS,OFF) of the hyper-FET in comparison to the stand-alone MOSFET, whereas the reduction in ON-state current (IDS,ON) is much less significant since the voltage drop across the metallic VO2 is small; this results in an overall enhanced current change that is, a higher IDS,ON/IDS,OFF ratio (see Supplementary Fig. 3 and Supplementary Note 3 for additional details and simulations). We model the MOSFET with VO2 combination as an equivalent common-source transistor circuit (Fig. 2a) where:
Here, gm is the transconductance of the stand-alone MOSFET. Across the IMT, the VO2 exhibits an NDR (=−ΔVNDR/ΔIDS), and therefore equation (1) evolves to:
Equation (2) indicates that in a particular gate-voltage window, the amplified differential transconductance (βgm; β>1) of the hyper-FET facilitates a larger change in current compared with the stand-alone MOSFET. The VO2, therefore, sets up an internal amplifier (β>1) in the hyper-FET, and the transconductance enhancement (βgm) is directly related to the free-carrier amplification across the phase transition. We note that although the hyper-FET has reduced transconductance before and after the IMT (that is, VO2 in the stable insulating/metallic state), the abrupt free-carrier amplification across the IMT overcompensates this reduction and enables an amplified current change. To evaluate the improved performance of the hyper-FET, particularly for digital-logic applications, we match the OFF-state current IDS,OFF of the hyper-FET and the stand-alone MOSFET and analyze the increase in ON-state current IDS,ON over the operating gate-voltage window, as shown further.
Low-voltage n-type and p-type hyper-FET operation
Next, we focus on the MOSFET component of the hyper-FET. The gate-bias triggers the phase transition in VO2 by enabling the MOSFET to source the corresponding critical currents. Therefore, using a scaled transistor can enable low-voltage hyper-FET operation since the transistor can now source the same currents at low VGS and VDS. This motivates the integration of scaled, high-gm-advanced transistor architectures like FinFETs fabricated on channel materials having mobilities higher than that of silicon to design a low-voltage hyper-FET (Figs 3 and 4).
Figure 3a illustrates a scaled hyper-FET consisting of a scaled In0.7Ga0.3As quantum-well multi-channel FinFET (Lg=500 nm) (see Supplementary Fig. 4 and Supplementary Note 4 for fabrication method) in series with VO2 (=200 nm; =1 μm). Figure 3b shows the transfer characteristics of the hyper-FET (and the stand-alone FinFET) exhibiting a ‘gate controlled’ abrupt turn-ON/turn-OFF associated with the IMT/MIT in VO2, respectively. The direct comparison of the hyper-FET with the stand-alone FinFET reveals an improved IDS,ON/IDS,OFF ratio over a VGS range of 0.8 V, and thus a ∼20% enhancement in IDS,ON at matched IDS,OFF (Fig. 3c). The corresponding output characteristics of the hyper-FET and its constituent FinFET, shown in Fig. 3d, also reflect the IDS enhancement.
We also demonstrate a p-type hyper-FET since complementary operation, similar to the complementary metal-oxide-semiconductor (CMOS) logic family, is imperative for low standby-power digital applications. Two-terminal VO2 devices exhibit reversible switching in both positive and negative voltage polarities (Supplementary Fig. 1) which allows for electrical integration with a p-channel FinFET to enable p-type hyper-FET operation. Figure 4a shows the schematic of a p-hyper-FET constructed using a p-channel Ge quantum-well multi-channel FinFET (see Supplementary Fig. 4 and Supplementary Note 4 for fabrication method) in series with VO2 (=200 nm; =1 μm). Figure 4b,d shows the transfer characteristics and the corresponding output characteristics of the p-hyper-FET and its constituent FinFET, respectively. The p-hyper-FET also exhibits an enhanced ISD,ON/ISD,OFF ratio over a VGS range of −0.5 V, and thus a ∼60% enhancement in ISD,ON at matched ISD,OFF (Fig. 4c).
The hyper-FET is a device concept that harnesses the phase transition in the IMT material, VO2, to enable room temperature, steep-slope, n-type and p-type transistor operation with enhanced performance. These experimental results motivate the realization of a scaled, monolithic hyper-FET design entailing hetero-integration of the IMT material with the conventional FET44,45,46,47,48. Such an integrated device would have to include careful design considerations for minimizing the device ‘foot-print’44, reducing potential self-heating effects as well as ensuring low-contact resistance of both the conventional MOSFET, which can adversely affect its ON-state current (and therefore that of the hyper-FET), and that of the VO2, which may possibly affect the magnitude of abrupt current change across the IMT. Further, scaling and optimizing the VO2 and the MOSFET properties to enable a scaled hyper-FET device with low OFF-state leakage current relevant to low-power circuit applications49, and reduced hysteresis with a complete rail-to-rail swing in a complementary configuration (some of the design considerations are discussed in Supplementary Note 5 and Supplementary Fig. 5) will be key factors in realizing a hyper-FET-based hardware platform that can augment current state-of-the-art technology49.
The hyper-FET, demonstrated here, is a manifestation of a design methodology that consolidates the unique properties of phase transition materials like abrupt and reversible resistivity switching, arising from collective carrier dynamics and usually inaccessible in a conventional semiconductor, with the robust field-induced switching dynamics of a conventional MOSFET. Our approach harnesses the abrupt IMT in VO2 in the much-desired three-terminal transistor configuration, circumventing the need for direct electric field-induced phase transition. Furthermore, the generality of the hyper-FET design also facilitates this transistor architecture to be extended to other insulator–metal transition systems,50,51,52 thus opening the doors to using electronic phase transition materials in digital applications.
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This work was primarily supported by the Office of Naval Research through award N00014-11-1-0665 and Intel Corporation through a customized Semiconductor Research Corporation project at the Pennsylvania State University. This work was also supported, in part, by the Center for Low Energy Systems Technology (LEAST), one of six centres of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA.
The authors declare no competing financial interests.
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Shukla, N., Thathachary, A., Agrawal, A. et al. A steep-slope transistor based on abrupt electronic phase transition. Nat Commun 6, 7812 (2015). https://doi.org/10.1038/ncomms8812
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