On-chip detection of non-classical light by scalable integration of single-photon detectors

Photonic-integrated circuits have emerged as a scalable platform for complex quantum systems. A central goal is to integrate single-photon detectors to reduce optical losses, latency and wiring complexity associated with off-chip detectors. Superconducting nanowire single-photon detectors (SNSPDs) are particularly attractive because of high detection efficiency, sub-50-ps jitter and nanosecond-scale reset time. However, while single detectors have been incorporated into individual waveguides, the system detection efficiency of multiple SNSPDs in one photonic circuit—required for scalable quantum photonic circuits—has been limited to <0.2%. Here we introduce a micrometer-scale flip-chip process that enables scalable integration of SNSPDs on a range of photonic circuits. Ten low-jitter detectors are integrated on one circuit with 100% device yield. With an average system detection efficiency beyond 10%, and estimated on-chip detection efficiency of 14–52% for four detectors operated simultaneously, we demonstrate, to the best of our knowledge, the first on-chip photon correlation measurements of non-classical light.

in the main text. The bias current (IB) on the horizontal axis was normalized by the maximum bias current (switching current ISW) of the detector. The relative error of the SDE value is ±10% and the relative error of the ODE values is ±11.4%. (b) Photocount rate in counts per second vs. incident photon flux for the detectors A1, A2, B1 and B2. The detectors were biased at the operation point marked by circles in (a). For the measurements shown in  in the main text the average photon flux was kept at ~10-15 million photons per second, which was well within the single-photon regime of the detectors. Supplementary Figure 13. (a) Histogram of relative change in room-temperature detector resistance after membrane undercut compared to the resistance values before membrane undercut (suspension). (b) Critical current of detectors that were successfully transferred onto a secondary substrate on ~300-nm-thick SiNx membranes. Up to four thermal cycles were performed between ~2.8 K and room temperature.  Table 1. Calculated inductance values for series-2-SNAPs based on 80-nm-wide nanowires. These values were used to design the detectors. For each 2-SNAP, we need > 3*Lkin of a single section in series to ensure that the detectors have a broad avalanche regime of at least 20% of the switching current of an unconstricted SNAP (see Supplementary Ref. [6] for more details). Since every 2-SNAP has already three 2-SNAPs in series (3*1/2* Lkin of single section), we only need to add LS ≥ 1.5*Lkin of a single section as series inductor.

Supplementary Discussion
Effect of membrane fabrication and thermal cycling on SNSPDs. Before transferring membranes onto the PIC, we characterized the room-temperature resistance R after of detectors suspended on membranes and compared to detector resistance values R before before the substrate was removed. Supplementary Figure  13(a) shows that the relative detector resistance change (R after -R before )/R before was 1-2%, indicating no significant material damage to the detectors due to the membrane fabrication process. Supplementary  Figure 13(b) shows the critical current of membrane-detectors that were successfully transferred onto a secondary substrate. The membranes here consisted of ~300-nm-thick SiN x . The critical currents of detectors on 300-to 400-nm-thick membranes were suppressed by ~10% compared to values measured on the solid substrate before undercut, while critical currents of detectors on sub-200-nm-thick membranes were suppressed by ~10-20%. Due to the small change in room temperature resistance values (Supplementary Figure 10(a)) we attribute the critical current suppression to the lower thermal capacity of the membranes compared to a solid substrate. Thermal cycling did not result in a measurable degradation (within the measurement accuracy of ~0.5 µA) of critical current of the transferred detectors.
Dependence of system dark count rate on shielding conditions. We used a closed-cycle cryostat with optical access to operate the chip shown in Figure 1(b) in the main text. The schematic cross-section of the cryostat is shown in Supplementary Figure 14(a). The PIC chip and platform holding the micro-manipulated lensed fibers were kept at 3 K base temperature. In order to couple light from the lensed fibers into the waveguides, the edges of the chip, containing the polymer couplers (Figures 1(c-I, c-II) in the main text), were imaged through the windows using a 50x long-working-distance objective. The direct imaging greatly simplified pre-alignment, while finer fiber-to-coupler alignment was performed using feedback from the on-chip detectors. However, the optical access ports in this prototyping setup resulted in radiation leakage and therefore increased the system dark count rate of the detectors significantly, as shown in Supplementary  Figure 14(b). When we replaced the 30 K window in the cryostat with a solid copper plate, we observed a significantly lower dark count rate of ~ 5 kcps instead of ~ 800 kcps at the operation point.

Improving detection efficiency and jitter.
For low-jitter detectors, the detection efficiency is limited by the optical absorption [7]. The optical absorption can be improved further by increasing the detector-towaveguide coupling length. Supplementary Figure 15(a) shows a detector integrated with a 500-nm-wide silicon waveguide as outlined in the main text. This detector has a coupling length of 28 µm (compared with 16-17 µm for the detectors in the main text). We integrated these detectors with an on-chip directional coupler as shown in Supplementary Figure 1(c). Supplementary Figure 15(b) shows the system detection efficiency vs. noise-equivalent incident power for these waveguide-integrated detectors. The increased coupling length resulted in a system detection efficiency up to 24 ± 2%, an improvement by ~ 26 ± 3% compared to the previous detector design with shorter coupling length. The timing jitter of the waveguideintegrated detectors is limited by the signal-to-noise ratio of the detector pulse, which can be improved by decreasing losses in the RF lines. We demonstrated this limiting factor by reducing the length of the RF line by 1 cm and the length of our wire-bonds onto the Au pads by 3 mm. The shorter electrical path resulted in a FWHM timing jitter of 33 ps, as shown in Supplementary Figure 15(c), a significant improvement compared to ≥42 ps jitter previously measured in the same cryostat.

Supplementary Methods
Optical Simulations. We used a finite-element model to calculate the length of the detector that would provide sufficient absorption of the mode travelling in the waveguide. The simulated geometry, superposed by the electromagnetic mode profile, is shown in Supplementary Figure 2(a). In this work, we consider only the fundamental TE mode; we experimentally observe no noticeable conversion from this mode to other waveguide modes. The detector was separated from the surface of the waveguide by residual resist layers used to fabricate the detector and the waveguide. We estimated the thickness of the residual resist layer as 20 to 80 nm. The 2D finite element simulations, performed in COMSOL, were used to calculate the imaginary part of the effective mode index n i . Following Supplementary Ref. [1], we calculated the optical absorption α in the detector as 1 exp 4π ⋅ ⋅ / 1.55 , where is the detector (coupling) length in µm. Based on the calculated absorption in the detector, shown in Supplementary Figure 2(b), we chose 17 µm to ensure α > 50 %. In practice, we measured optical absorption values of 62 -74 %. The optical absorption could be further increased by increasing [2]. There are two main experimental factors besides detector length that limit the practically achievable detector absorption: misalignment and scattering at the interface of the SiN x detector membrane. We show in Supplementary Figure 3(a) the effect of misalignment on absorption. The detector region is 1.5 µm wide, but only nanowires directly above the waveguide have appreciable overlap with the waveguide mode. Therefore, within the detector active area, the absorption is roughly periodic as a function of horizontal displacement with a period of 200 nm, the nanowire pitch. Even at 100 nm misalignment the absorption is reduced by only 0.8%. For this simulation, we assumed 80 nm resist and a 200 nm SiN x membrane. We calculate the transmission at the SiN x membrane edge using coupled mode theory. is therefore calculated using an overlap integral defined as , which gives the fraction of power transmitted from the silicon waveguide with air cladding to the silicon waveguide with SiN x cladding. For our experimental conditions, 1%. The perturbation is this small because the silicon nitride is thin, the index of silicon nitride is significantly lower than that of silicon, and the resist spacer layer on the silicon waveguide decreases the mode of overlap with the silicon nitride. We plot the mode pattern with and without the SiN x cladding in Supplementary Figure 3(b).
Nanowire circuit. The waveguide-detectors consisted of four units connected in series, with each unit comprising two ~80-nm-wide nanowires (200 nm pitch) in parallel. Detectors comprising this parallelnanowire structure are commonly referred to as superconducting nanowire avalanche photodetectors (SNAPs [3,4]). This detector design, illustrated in Supplementary Figures 1(a, b), is similar to detectors in Supplementary Ref. [5]. The value of the series inductor L S was generally chosen as ~ 50 nH so that the total inductance in series with a single parallel-nanowire unit was about 3-to 7-times the series inductance of a single nanowire (see Supplementary Ref. [6]). The detailed inductance values are listed in Supplementary Table 1.
Membrane layout. Supplementary Figure 4(a) shows a basic (initial) design of a suspended membranedetector, connected to the bulk substrate via four ~15-µm-long microbridges. These bridges had an unpredictable breaking pattern (Supplementary Figure 4 Figure 5(c)). Initially the protective etch mask that was used to fabricate the trenches via reactive ion etch (RIE) with CF 4 was also used as a protective layer in the subsequent etch step with XeF 2 . The fluorine gas (plasma) treatment during the RIE fluorinated the surface and hard-baked the resist, making it irremovable in solvents unless ultrasonic agitation was used. However, sonication could not be used after membrane undercut since it was found to cause membrane collapse. Oxygen-helium plasma (ashing) was the remaining option, but we could not remove the hard-baked residue after ashing, shown in Supplementary Figure 9(b). We solved this issue by removing the resist mask after the trenches were fabricated via sonication ('photoresist 1' in Supplementary Figure 5(b)), and coating the detectors with a new resist mask for the silicon removal step ('photoresist 2' in Supplementary Figure 5(c)). Since the second mask was not exposed to a long CF 4 etch, we were able to remove it in an NMP-based resist stripper followed by an acetone and IPA rinse. While requiring an additional photolithography step, this stripping process did not leave a visible residue on the nanowires, as shown in Supplementary Figure 12(c).