Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air–SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand.

Second, the analysis of the triboelectric series for SiO 2 , Pt and graphene reveals that our results may not be explained by the friction of graphene and SiO 2 . In order to determine the relative positions of SiO 2 and Pt in the triboelectric series, we rubbed SiO 2 (300 nm) over a 2 × 2 μm 2 area using a grounded Pt-coated AFM tip in contact mode and measured the surface potential (5 × 5 μm 2 ) both before and after triboelectrification, similar to the experiments shown in Fig. 1. Supplementary Fig. 3a shows the uniform surface potential of SiO 2 before rubbing. Supplementary Fig. 3b shows that, after rubbing, the surface potential of the rubbed region decreased contrastively to results in Fig. 1c which shows an increased surface potential in the rubbed region. As a consequence, Pt is positive with respect to SiO 2 in the triboelectric series. In case of friction between Pt and graphene ( Supplementary Fig. 3d), the sign of the triboelectric charges is determined by the work functions (Φ) of the two materials.
In practice, after friction, electrons transfer from graphene (Φ Graphene ≈ 4.5 eV) to Pt (Φ Pt ≈ 5.9 eV) and then, graphene becomes positive and Pt becomes negative. The resulting triboelectric series of SiO 2 , Pt, and graphene is schematically described in Supplementary Fig. 3f, so that, in the hypothetical case of friction between SiO 2 and graphene, SiO 2 would become negative and graphene positive ( Supplementary Fig. 3e), contrary to our experimental results.
In conclusion, both the absence of detectable effects when using mechanically exfoliated graphene and the triboelectric series of SiO 2 , Pt, and graphene confirm that the localization of charges on the insulator underneath graphene is not induced by friction between graphene and SiO 2 , but is determined by the tunneling of triboelectric charges generated by friction between the Pt-coated AFM tip and graphene.

Localization of charges at the air-SiO 2 interface
In principle, the triboelectric charges might also be trapped in the defects or impurities of CVD graphene rather than being stored at the air-SiO 2 interface. In fact, this is possible during a very short transient, but this mechanism may not justify the very slow decay of the potential difference between the rubbed and unrubbed graphene areas (e.g. see Fig. 1d, 1e and Supplementary Fig. 4). Additional charges trapped in graphene defects or impurities would create potential differences in graphene, but, since CVD graphene is not insulating, these potential differences would immediately result in currents which would tend to make graphene equipotential. In CVD graphene, different from insulators, these processes would be extremely fast (i.e. in conductors or semiconductors, significant potential differences may not be maintained for long times in absence of an external perturbation). In other words, after a very fast transient, potential differences across the CVD graphene (similar to other conductors or semiconductors) would quickly disappear.
By contrast, the existence, for very long times (e.g. many days), of potential differences in graphene is easily explained by the presence of electric charges localized on an insulator underneath graphene, similar to MOS (metal-oxide-semiconductor) capacitors, the difference being that our gate is floating, immaterial, and re-writable (i.e. time variant). The localization of charges at the air-SiO 2 interface is also confirmed by the accuracy of the equivalent circuit shown in Fig. 2d, which gives reasons of the presence of a shorter time constant (associated to the discharge of the oxide capacitor) and of a longer time constant (associated to the discharge of the air-gap capacitor) as well as of the higher magnitude of the slow-decay term (almost all the charges localize on the air-gap capacitor rather than on the SiO 2 capacitor, see main text). We mention that the localization of the charges at the air-SiO 2 interface is also confirmed by the Dirac point shift (Supplementary Note 4 and Supplementary Fig. 13).

Triboelectrification of graphene on different substrates
As an additional confirmation, in order to further verify that charges are trapped at the air-gap SiO 2 interface, we also carried out identical experiments with conductive metal substrates.
The CVD graphene sheet was transferred on copper (Cu) substrates was treated by HF to remove the native oxide layer ( Supplementary Fig. 5). Then, the top surface of graphene was rubbed with the Pt-coated AFM tip and the surface potential was measured using KPFM. In contrast with the case of insulating substrates, triboelectric charges were not localized in the rubbed region (white dashed square) but spread to the whole region ( Supplementary Fig. 5c), thus confirming that the presence of an insulator under graphene is crucial.
Moreover, we also repeated the same experiments with CVD graphene deposited on other insulating substrates such as mica and Al 2 O 3 (see Supplementary Fig. 6) and, similar to the case of CVD graphene on SiO 2 , found that charges, after tunneling through CVD graphene, were trapped at the interface between air-gap and SiO 2 .

Fundamentals on charges stored on two series capacitors
In general, series capacitors may have a non-zero net charge on their two adjacent plates (a similar situation can be found in switched-capacitor circuits where, assuming the input op amp currents can be neglected, during some periods, two capacitors can be considered as in series even if the net charge on their two adjacent plates is non-zero). For this reason, with reference to the circuit shown in Supplementary Fig. 8 it is, in general, impossible to determine the DC voltages across C 1 and C 2 (e.g. circuit simulators such as SPICE would not be able to predict the DC voltage V X in the circuit in Supplementary Fig. 8, but would simply warn that node X is floating).
With reference to the circuit shown in Supplementary Fig. 8, the charges associated to the capacitor C 1 are +Q 1 and -Q 1 and, similarly, the charges associated to the capacitor C 2 are +Q 2 and -Q 2 . In general, we may not assume +Q 1 and +Q 2 are identical (i.e. we may not assume the net charge on the adjacent plates of C 1 and C 2 , i.e. Q 2 -Q 1 , is zero). This is certainly possible and would, in fact, be the case if, at a certain instant t X , V B is equal to zero and both the capacitors are fully discharged (i.e. both +Q 1 and +Q 2 equal to zero); in such case, at t X , the net charge on the adjacent plates of C 1 and C 2 , i.e. Q 2 -Q 1 , would obviously also be zero; therefore, due to the conservation of charge, if the voltage V B changes, since, ideally (i.e. neglecting leakage currents), no charge can flow through dielectrics, the net charge on the adjacent plates of C 1 and C 2 , i.e. Q 2 -Q 1 , will be equal to zero for ever. As a result, in this specific case, by imposing Q 2 = Q 1 we would find the well-known relation Such a relation is, however, not true if the net charge on the adjacent plates of C 1 and C 2 , i.e.
The following fictitious experiment, schematically represented in Supplementary Fig. 9, shows that the net charge on the adjacent plates of C 1 and C 2 , i.e. Q 2 -Q 1 , can be different from zero. For simplicity, we consider ideal capacitors (e.g. we neglect leakage), ideal switches (e.g. infinite off-resistance and zero on-resistance) and two given voltages (9 V and 1V, without any loss of generality as the same discussion applies for arbitrary voltages); moreover, we assume that C 1 and C 2 are identical (C 1 = C 2 ). With such assumptions, consider the following experiment: a) C 1 is charged to 9 V by a 9 V DC voltage source ( Supplementary Fig. 9a, switches S 1A closed and all the other switches opened) b) C 1 is disconnected from the DC voltage source and C 2 is charged to 1 V by a 1 V DC voltage source ( Supplementary Fig. 9b, switches S 2B closed and all the other switches opened); the voltage across C 1 will stay constant at 9 V because C 1 , after disconnection from the 9 V voltage source, is in series with an open circuit (i = 0) and, therefore, according to the constitutive capacitor equation dv iC dt  , its voltage must be constant and equal to 9 V c) All the switches are opened ( Supplementary Fig. 9c) so that both the capacitor voltages will stay constant at 9 V (C 1 ) and 1 V (C 2 ), respectively (both capacitors are connected in series with an open circuit) d) The switch S 3C is closed ( Supplementary Fig. 9d) and, therefore, connect in series the capacitors C 1 and C 2 ; during this step, at all times, each capacitor is in series with an open circuit and, therefore, the voltages across both C 1 and C 2 will stay constant and equal to 9 V and 1 V, respectively, which obviously corresponds to different values for the charges Q 1 and Q 2 (we assumed C 1 = C 2 , so if the voltages are different, the charges are different), i.e. to a net charge on the adjacent plates of C 1 and C 2 , i.e. Q 2 -Q 1 , different from zero.

Distribution of charges after tunneling triboelectrification
With reference to the two small-area series capacitors in Fig. 2d, after tunneling triboelectrification, the net charge on the adjacent plates of the two capacitors (i.e. the tunneling triboelectric charges trapped in the insulator) is certainly not zero. In fact, the existence of a significant potential difference within the graphene layer for very long times However, it is easy to see that almost all the tunneling triboelectric charges, Q TT (i.e. a fraction, which may be close to one in case of 1L CVD graphene, of the triboelectric charges), are stored on the small-area air gap capacitor. In fact, after tunneling through graphene, the charges Q TT are trapped at the interface between air and SiO 2 and, therefore, electrostatically attract an equal amount (magnitude) of charges of the opposite type on the graphene layer and/or on the silicon underneath silicon oxide. In other words, with reference to Fig. 2d, since charges may not travel through dielectrics, the charges Q TT must be stored on the top plate of the SiO 2 small-area capacitor and/or on the bottom plate of the small-area air capacitor.
However, as graphically illustrated in Fig. 2d As a result, by considering the air gap thickness t Air ( Supplementary Fig. 2), we easily estimate the charge density (Fig. 3e) stored underneath graphene in (x,y) as where ∆V TT is the surface potential measured (by KPFM) in the point (x,y) taken with reference to the average surface potential of the unrubbed region (see main text), ε Air is the dielectric constant of air and t Air is the thickness of air gap.

Decay time of ∆V TT
In the hypothetical circuit shown in Supplementary Fig. 10a, the two capacitors C 1 and C 2 are in parallel (each capacitor connects the same couple of terminals). The two parallel capacitors C 1 and C 2 could, therefore, also be represented as a single capacitor with capacitance C 1 +C 2 ; as a result the discharge of the capacitors would be exponential with a single time constant equal to (R 1 //R 2 )(C 1 +C 2 ), where R 1 //R 2 is the parallel of R 1 and R 2 , i.e. R 1 R 2 /(R 1 +R 2 ).
However, in case of tunneling triboelectrification, after the equilibrium has been reached, there is no current across graphene, thus resulting in the equivalent circuit shown in Supplementary Fig. 10b. As a consequence, due to Kirchoff's current law (i.e. conservation of charge), there may be no current going from the top bipole (parallel connection of R 1 and C 1 ) to the bottom bipole (parallel connection of R 2 and C 2 ). Therefore, the capacitor C 1 may only discharge through the resistor R 1 , thus resulting in a time constant R 1 C 1 ; similarly, the capacitor C 2 may only discharge through the resistor R 2 , thus resulting in a time constant R 2 C 2 , in perfect agreement with our experiments (e.g. see the excellent agreement between experimental points and the best fit in Fig. 1e). As a result, the total voltage (measured by KPFM) will evolve with time as where V 1 is the initial voltage (at t = 0) across C 1 , V 2 is the initial voltage (at t = 0) across C 2 , In practice, in case of tunneling triboelectrification, one of these two addends dominates at all times as it has both a higher initial magnitude and a longer time constant. In fact, the higher initial magnitude is certainly associated to the air gap capacitor because almost all the tunneling triboelectric charges are localized across the air gap capacitor (see main text and Supplementary Note 3.2); additionally, air is a much better insulator than silicon oxide and, therefore, the time constant associated to the air gap capacitor is much longer than the time constant associated to the SiO 2 capacitor.
These results are in perfect agreement with all our experiments and give reasons for the exceptionally long time constants we found after tunneling triboelectrification (more than two orders of magnitude longer than for conventional triboelectrification of a dielectric).

Resistance control on CVD graphene resistor
Supplementary Fig. 12 shows the resistance reduction induced on the 4-contacts 1L CVD graphene resistor shown in Fig. 4. In practice, as schematically shown in Supplementary Fig.   12a, we performed 4-wires measurements by injecting a 100 nA current through the force electrodes F 1 and F 2 and measuring the voltage difference across the inner sense electrodes S 1 and S 2 (the instrumentation amplifier IA has negligible input currents and, therefore, first, the entire I 0 current flows through the graphene resistor R G , and, second, the voltage across the input terminals of the instrumentation amplifier is exactly the same as the voltage across R G ).
For instance, Supplementary Fig. 12b-d show the voltages across R G (i.e. 100 nA × R G ) before (higher value of R G and, therefore, of the voltage difference across R G ) and after rubbing the middle area (yellow dashed box, between the sense electrodes S 1 and S 2 in Fig.   4a) with an AFM-Pt tip biased at -10 V (b), -5 V (c), and 0 V (d), respectively. As evident, the tunneling triboelectric charges act as ghost floating gates and electrostatically reduce the normalized resistance R/R 0 (where R is the resistance of graphene after rubbing and R 0 is the resistance before rubbing). These results already constitute a device-level demonstration of tunneling triboelectrification (e.g. tunable resistors are useful in tunable amplifiers, automatic gain control circuits, tunable voltage/current references, etc.).

Dirac point shift by tunneling triboelectrification
In addition to the control of graphene resistivity by tunneling triboelectrification (Fig. 4 and Supplementary Fig. 12), we also verified that tunneling triboelectrification allows to control the Dirac point of graphene ( Supplementary Fig. 13). In practice, we measured the drain-tosource current (I DS ) of a graphene resistor as a function of the back gate voltage (V BG ) both before and after rubbing p-doped graphene with an AFM tip biased at +10 V. The I DS -V BG curves were measured under constant drain-to-source voltage (V DS = 0.01 V). As described in Supplementary Fig. 13b, after tunneling triboelectrification, the Dirac point of the graphene resistor shifts to the left and, with a zero gate voltage, the effective doping turns from p-type to n-type. In fact, consistently with our theoretical discussions, first, positive charges are generated in graphene by triboelectrification with the positively biased AFM tip and, second, part of these positive charges tunnel through the air gap and effectively turn the naturally ptype graphene into n-type ( Supplementary Fig. 13a). This situation is exactly the same found in MOS (metal-oxide-semiconductor) capacitors where the presence of charges on the metal gate induces opposite charges on the semiconductor and, therefore, travelling through the semiconductor at the semiconductor-oxide interface, going from the region underneath the gate to the surrounding regions of the semiconductor, there are potential differences (due to the gate charges) which may be well preserved for very long times. This is exactly analogous to our case, the difference being that our gate is floating, immaterial, and re-writable (or, equivalently, time variant). In conclusion, Supplementary Fig. 13b confirms that tunneling triboelectrification can effectively control the current transport characteristics of 2D devices.
We mention that Supplementary Fig. 13b  on CVD graphene which has localized charges under graphene (bright region in the center of the CVD graphene). The localized tunneling triboelectric charges were well preserved after applying V ext = 2 V, but were completely erased after applying V ext =