Three-dimensional crossbar arrays of self-rectifying Si/SiO2/Si memristors

Memristors are promising building blocks for the next-generation memory and neuromorphic computing systems. Most memristors use materials that are incompatible with the silicon dominant complementary metal-oxide-semiconductor technology, and require external selectors in order for large memristor arrays to function properly. Here we demonstrate a fully foundry-compatible, all-silicon-based and self-rectifying memristor that negates the need for external selectors in large arrays. With a p-Si/SiO2/n-Si structure, our memristor exhibits repeatable unipolar resistance switching behaviour (105 rectifying ratio, 104 ON/OFF) and excellent retention at 300 °C. We further build three-dimensinal crossbar arrays (up to five layers of 100 nm memristors) using fluid-supported silicon membranes, and experimentally confirm the successful suppression of both intra- and inter-layer sneak path currents through the built-in diodes. The current work opens up opportunities for low-cost mass production of three-dimensional memristor arrays on large silicon and flexible substrates without increasing circuit complexity.

EELS mapping for oxygen element shows a protrusion area with almost no oxygen and a channel connecting two electrodes with less oxygen, which we believe is the conduction channel. c, The EELS mapping for silicon element shows the protrusion found in the oxygen mapping is made of silicon. However, the channel found in oxygen mapping is not clear. d. The EELS mapping for zero valence silicon shows noticeable zero valence silicon constructing the channel, confirming the channel is Si 0 rich. (Spatially resolved spectra of Si L2,3 edge are presented in Figure 3 in the main text.). Scale bar, 10 nm. Figure 5 | Crossbar array size estimation. a, The circuit used in the SPICE simulation for the array size estimation. The wire resistance between each memristor node is between 0 Ω and 1000 Ω in the following simulation. The voltage is applied on the far corner device, so that there will be the most significant impact from wire resistance. b, The circuit schematic used during the calculation of readout margin, where a pull-up resistor is connected in series with the crossbar array, and the states of the accessed device was read by sensing the voltage drop on the pull-up resistor. c, The readout resistance of the selected device in a crossbar array with different size capacity and wire resistance. The HRS resistance decreases with array size due to larger sneak path current, while the LRS resistance increases with the wire resistance, because the wire resistance becomes more significant than cell resistance itself. Figure 6 | SPICE simulation for the array size estimation with different read out schemes. a, The floating scheme. The voltage is applied across the selected word and bit line while all other word and bit lines are floated. The blue staircase line shows one possible sneak path in this scenario which includes one reverse biased cell and two forward bias cell. The cells in red color are reverse biased, which suppress the sneak path current. b, The half voltage bias scheme. In this case, the voltage is applied across the selected word and bit line while all other bit and word lines are half voltage biased. In this case, the cells in yellow color are half biased. The half biased cells suppress the sneak path current, because of its nonlinear forward IV relation. c, The one-third voltage bias scheme. In this case, the selected word line is fully biased while the selected bit line grounded. The unselected word lines and bit lines are biased at 1/3 and 2/3 of the full bias voltage respectively. d, The readout resistance of the selected device in a crossbar array shows that the readout ON/OFF resistance ratio is larger if the 1/3 voltage bias scheme is used. e, The normalized readout margin with different size capacity and read scheme, which shows the readout margin can be improved by using the one-third bias scheme. In the simulation, the wire resistance between each cell node of 1 Ω is assumed.

Supplementary Figure 7 | Two layers of stacked p-Si/SiO2
/n-Si crossbar memristors array. a, SEM image of the 2-layer stacked 8×8 memristors array. For the 1 st layer (bottom layer) structure, only the measurement pads can be clearly seen in this image as other parts are buried inside of the interlayer dielectric. Scale bar, 100 μm. b. The zoomin area of the SEM image for the crossbar devices. c. The readout current at +2V for the 2 layers stacked memristors which were programmed into "umass" and "amherst" respectively. All other cells were programmed into LRS to emulate the worst-case scenario with maximum sneak path current. Scale bar, 10 μm.

Supplementary Figure 8 | Cross-sectional TEM image of the 3D stacked Si/SiO2/Si memristor crossbar arrays.
a, The annular dark-field (ADF) STEM image of the cross-sectional TEM image of the 6 layers of the stacked Si that made 5 layers Si/SiO 2 /Si memristor crossbar arrays. The top protective Pt layer and the bright rings in the lower layer was deposited during the TEM sample preparation with FIB using a gas injection system. The brighter color of Pt material in the ADF-STEM image indicates more conducting property, and the 5 th Si layer is blocked by the Pt deposited during FIB in this image because of a slight misalignment to lower layers. The voids closer to the surface were filled up by Pt because the gas is coming from the surface area, and the holy 3D structure is permeable to the gas precursor. Scale bar, 200 nm. b, HRTEM image of the first 2 layers of the 3D Si/SiO 2 /Si cross bar, corresponding to the area marked in the square area in a. About 5 nm amorphous SiO 2 is sandwiched between the adjacent Si layers. The dark dotted rings in the voids in the HRTEM image are the Pt, which is corresponding to the bright rings in the ADF-STEM image in a. The darker color indicates higher atomic ratio in the HRTEM image. Scale bar, 20 nm.  Fig. 1 is the schematic illustration of the fluid-supported membrane transfer procedure we used for our device fabrication. First, the silicon device layer on one SOI wafer was pattern into mesh structure to expose the buried oxide (BOX), which was then etched with concentrated hydrofluoric (HF) acid (Supplementary Figs. 1a, 1b). After the BOX layer was

Supplementary Table 1 | Comparison of the performance of self-rectifying memristors in recent reports
fully removed the SOI wafer was immersed into deionized (DI) water in another beaker. Since the silicon membrane was hydrophobic after HF etching, it was thus peeled off from the SOI wafer by capillary force in the DI water (Supplementary Fig. 1c). The floating membrane was then transferred to another substrate by picking it up from the beaker (Supplementary Fig. 1d).
Moisture was removed by nitrogen blow dry and baking on a hotplate at 110 °C for 5 min. After baking, the collected membrane cannot be separated from the substrate by DI water washing or ultrasonic treatment in acetone, which suggests a strong bonding formed between the two contacted silicon surfaces. The top electrode made of transferred membrane was then patterned by photolithography and dry etch.
It is noteworthy that we can achieve high fabrication yield in the large-area silicon membranes transfer. Supplementary Figs. 2a-2d are optical microscope images for a patterned SOI wafer during the releasing process. The BOX was gradually removed as the etching progressed. Supplementary Fig. 2e shows a square silicon membrane with dimension of 0.75 cm×0.75 cm floating on the DI water in a beaker. Larger membranes are possible with a larger pre-patterned area on the SOI wafer. The silicon membrane can also be stored in a water filled box (shown in Supplementary Fig. 2f) for future use.

Supplementary Note 2: Additional electrical measurements
Our p-Si/SiO2/n-Si memristive device can also be repeatedly programmed with electrical pulses. Voltage pules were applied to the devices and the currents were measured simultaneously to monitor when the devices were switched. For example, a 5×5 μm 2 device was RESET to HRS with a 5 ms/5.5 V pulse and SET to LRS with a 5 ms/9 V pulse (Supplementary Fig. 3a) applied on the top electrode (p-Si). The resistance states were read with 5 ms/2 V pulses that cannot change the device state. The RESET and SET voltages are higher than those measured with DC sweeps (VRESET=4.5 V, VSET=7.5 V at DC). Supplementary Fig. 3b shows 25 consecutive cycles of the pulse switching, with current read under 5ms/+2V (forward) and 5ms/-2V (reverse) voltage pulses on the top electrode after each write operation. It is clear that the reverse current was suppressed regardless of the resistance state of the device.

Supplementary Note 3: SPICE modelling and simulation for array size estimation
The SPICE model of our all silicon resistive switching device is written in Verilog-A language.
The following code snippet describes the voltage-current relation in each state: A resistor of 550 Ω is also added in series with the above described modelling device in order to reflect the measured series resistance within the device cell. The SPICE model well fits the measurement data, as is shown in Fig. 4c in the main text.
We first use floating scheme to read the resistance state of the selected cell in a crossbar array during the simulation. In this scheme, the cell state is read by applying voltage across the selected word and bit lines with all other lines floated. An illustrative 4×4 crossbar array that demonstrates the simulation algorithm is shown in Supplementary Fig. 5a. For all the readout simulation, the worst-case scenario is considered as follows: 1. The voltage is applied on the far most cornered device, so that the current goes through the largest wire resistance. 2. All the unselected devices are in LRS, so that the sneak path current is the largest among all the cases. A self-written python script is used to generate the netlist automatically for a large device array.
In the circuit operation, the resistance states are usually read by detecting the voltage across the pullout resistor (Supplementary Fig. 5b) So pull up resistance was chosen to be pu The readout resistance considering different wire resistance between each cells is plotted in Supplementary Fig. 5c. For the heavily doped Si (10 20 cm -3 boron doping, 0.001 Ω·cm resistivity) the sheet resistance for a 70 nm thick silicon wire is around 150 Ω/sq, and in the simulation we considered the wire resistance from 0 to 1000 Ω/sq. Larger readout resistance difference in different state will yield larger readout margin by sensing the voltage drop on the pull up resistor. The readout margin is shown in Fig. 4 in the maintext.
The readout margin can be further improved if we use different voltage bias schemes, although they may consume more power and involve more complicated circuit implementation than the floating one 13 . Here we show the comparison between floating (Supplementary Fig.   6a), half voltage bias (Supplementary Fig. 6b) and one-third voltage bias schemes (Supplementary Fig. 6c). The readout resistance for the selected cell in an array and the normalized readout margin for different read scheme in a different size of array are shown in