Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic

Recently, negative differential resistance devices have attracted considerable attention due to their folded current–voltage characteristic, which presents multiple threshold voltage values. Because of this remarkable property, studies associated with the negative differential resistance devices have been explored for realizing multi-valued logic applications. Here we demonstrate a negative differential resistance device based on a phosphorene/rhenium disulfide (BP/ReS2) heterojunction that is formed by type-III broken-gap band alignment, showing high peak-to-valley current ratio values of 4.2 and 6.9 at room temperature and 180 K, respectively. Also, the carrier transport mechanism of the BP/ReS2 negative differential resistance device is investigated in detail by analysing the tunnelling and diffusion currents at various temperatures with the proposed analytic negative differential resistance device model. Finally, we demonstrate a ternary inverter as a multi-valued logic application. This study of a two-dimensional material heterojunction is a step forward toward future multi-valued logic device research.


1) in
and the associated text in the manuscript, there seems to be no discussion about the origin for the values of (Ef-Ev) in BP and (Ec-Ef) in ReS2. Are those values measured, or cited from literature? The authors should clarify this point.
2) the high peak-to-valley current ratio (PVCR) is the highlight of this work, and it is very good that this manuscript reports 3 or more devices in total having high PVCR. Can the authors show some statistics of this important demonstration in the main Figure  Reviewer #2 (Remarks to the Author): 1. The author strongly states that the broken-band alignment of BP/ReS2 heterojunction is confirmed through the KPFM measurement. However, KPFM data shown in the manuscript only gives information on work function of each material, not on CBM and VBM. The author seems to complete the band structure of BP/ReS2 heterojunction (figure.1g) by utilizing the theoretically calculated data of reference 36 and 37, but I think those data are not fully matched to the 40nm BP and 50nm ReS2 (flakes utilized at the device). As the author has emphasized that the brokenband alignment is key factor to fabricating NDR easily, KPFM data seems not enough to prove that point 2. Figure. 1f seems too complicated, so it makes hard to figure out the data and explanation on the configuration of KPFM measurement.
3. 3. In the manuscript, experimental method on ternary inverter fabrication is not well-described. I suggest to add more explanation on the fabrication process and related experimental details General Review: In this paper, the author has fabricated a BP/ReS2 heterojunction based NDR device showing high PVCR value and also demonstrated ternary inverter as a multi-valued logic application. As the author has exhibited high-performance NDR device using 2D material and also conducted systematic analysis on its charge transport mechanism, I think this manuscript is valuable enough to be published just with minor tuning on the points mentioned above.
Reviewer #3 (Remarks to the Author): The manuscript presents an interesting study of negative differential resistance in black phosphorus/ReS2 heterojunction, and a demonstration of a multi-value logic (MVL) circuitry using one of the semiconductors as a transistor loaded by the tunnel diode. The material system chosen for this study is indeed new (Ref 5 reported a black phosphorus/SnSe2 tunnel diode with lower peak-to-valley-ratio); and the degree of NDR is improved from this earlier report. The MVL is old in traditional semiconductors, and is similar to the one reported in Ref 7. The results are indicative of heterojunction formation and interband tunneling; the models reported are able to explain the observed experimental work and are similar to prior (cited) work, and are not newly developed for this work.
The work is of high interest, and shows the richness of 2D layered material system choices. It improves on prior work (which is very important), the experiments and models presented here do not represent a new finding.
Some of the claims in the manuscript could be misleading and should be corrected in future versions: 1) In the introduction (page 4), it is claimed that "most NDR devices have shown very low PVCR .. at low temperatures... heterojunctions interfaces suffered significantly from defects...". This is incorrect. SiGe and III-V heterojunctions show robust, very high PVCRs at room temperature, much higher and more reproducible than what is reported in this manuscript and most 2D layered materials. Many of them are used in commercial devices, for example broken-gap III-V backward diodes are used for millimeter wave imaging applications. MVL logic has been demonstrated with 3D tunnel junctions, it just has not been very useful. These sorts of claims should be carefully considered because sometimes the 2D materials community do not do proper research of existing 3D semiconductor capabilities and make erroneous claims.
2) In page 4, the claim of " ... electrostatic doping ... " is incorrect. Any useful electronic device will need to be doped to be controlled; it does not help in adjusting threshold voltages etc if the doping is left to nature. This claim is repeated in page 6. This is a fundamental underestimation of the importance of doping in device physics.
3) Because the thickness of the BP layer is so high, how is the gating affecting the conductance? If it is changing the conductivity of the entire channel, it should reach in and also affect the band alignments, etc. This is not included in the analysis or model. 4) Page 6: PVCRs exceeding the reported values here by orders of magnitude have been observed in 3D semiconductor tunnel junctions.
5) The modeling in the supplemental material must provide the parameters that were used, they are missing.

Reviewer: 1 Comments to the Author
The authors in this manuscript reported a new heterojunction device with negative differential resistance (NDR), namely black phosphorous-ReS 2 van der Waals heterostructure. Although 2D-2D heterostructures with similar NDR behavior were reported before, as cited in this manuscript, the device performance here in terms of NDR behavior is best than anything in the literature. The amount of work reported here, such as the KPFM characterization, Raman spectroscopy, low temperature measurement, is comprehensive. The demonstration of the ternary inverter using the NDR diode based logic circuit highlights the potential of the BP-ReS 2 type III heterojunction. Overall, I think that this manuscript merits publication in Nature Communication. Addressing the following minor issues however, will increase the impact and the readership of this paper.
We would like to thank you for reviewing our paper; we appreciate your insightful comments on our research. We have revised the manuscript according to your suggestions and believe that the revisions have improved the paper.
Please find below our responses (in blue) to each specific comment (in black) provided by the reviewer. In addition, revisions to the original article are highlighted in red.
(1) In Figure 1g and the associated text in the manuscript, there seems to be no discussion about the origin for the values of (E f -E v ) in BP and (E c -E f ) in ReS 2 . Are those values measured, or cited from literature? The authors should clarify this point.

ANS:
We obtained the conduction band minimum (CBM), the valence band maximum (VBM), and the band gap (E g ) values of the BP and ReS 2 from previously reported literature [40][41][42] .
To clarify this point, we modified the following sentences and added the references in the article.
"Based on the obtained KPFM results and the previously reported band properties (conduction band minimum (CBM), valence band maximum (VBM), and band gap (E g )) of BP and ReS 2 40-42 , we graphically described the predicted energy band alignment of the BP and ReS 2 heterojunction at equilibrium before contact (Fig. 1g) and after contact (Fig. 1h). Here, the CBM, VBM, and E g values of the BP (ReS 2 ) that were calculated using a first-principles density of states in the literature were 4.2 eV (4.68 eV), 4.59 eV (6.05 eV), and 0.39 eV (1.37 eV), respectively." We also modified Figure 1g as below.
(2) The high peak-to-valley current ratio (PVCR) is the highlight of this work, and it is very good that this manuscript reports 3 or more devices in total having high PVCR. Can the authors show some statistics of this important demonstration in the main Figure instead of the supplementary information?

ANS:
As the reviewer suggested, we added the PVCR values for the three different BP/ReS 2 NDR devices in Figure 2b.
We also modified the following sentences in the article.
In the figure caption:

ANS:
As the reviewer suggested, we added the references as below: "It is also possible to design various heterojunctions by stacking different 2D materials with different bandgaps and electron affinities, where band structure alignment can be classified into three types: type-I (straddling-gap) 35 , type-II (staggered-gap) 2-4,6,7,31-34 , and type-III (broken-gap) 5,35 ."

Reviewer: 2 Comments to the Author
In this paper, the author has fabricated a BP/ReS 2 heterojunction based NDR device showing high PVCR value and also demonstrated ternary inverter as a multi-valued logic application. As the author has exhibited high-performance NDR device using 2D material and also conducted systematic analysis on its charge transport mechanism, I think this manuscript is valuable enough to be published just with minor tuning on the points mentioned above.
We would like to thank you for reviewing our paper; we appreciate your insightful comments on our research. We have revised the manuscript according to your suggestions and believe that the revisions have improved the paper.
Please find below our responses (in blue) to each specific comment (in black) provided by the reviewer. In addition, revisions to the original article are highlighted in red.
(1) The author strongly states that the broken-band alignment of BP/ReS 2 heterojunction is confirmed through the KPFM measurement. However, KPFM data shown in the manuscript only gives information on work function of each material, not on CBM and VBM. The author seems to complete the band structure of BP/ReS 2 heterojunction (figure.1g) by utilizing the theoretically calculated data of reference 36 and 37, but I think those data are not fully matched to the 40nm BP and 50nm ReS 2 (flakes utilized at the device). As the author has emphasized that the broken-band alignment is key factor to fabricating NDR easily, KPFM data seems not enough to prove that point.

ANS:
As the reviewer pointed out, we obtained only work function values of the materials through the KPFM measurement. We then referred to the conduction band minimum (CBM), the valence band maximum (VBM), and the band gap (E g ) values of the bulk BP and ReS 2 from previously reported literature 40-42 (Here, we added new references that reported the CBM, VBM, and E g values of bulk BP).
To clarify this point, we modified the following sentences and added the references in the article.
"Based on the obtained KPFM results and the previously reported band properties (conduction band minimum (CBM), valence band maximum (VBM), and band gap (E g )) of BP and ReS 2 40-42 , we graphically described the predicted energy band alignment of the BP and ReS 2 heterojunction at equilibrium before contact (Fig. 1g) and after contact (Fig. 1h). Here, the CBM, VBM, and E g values of the BP (ReS 2 ) that were calculated using a first-principles density of states in the literature were 4.2 eV (4.68 eV), 4.59 eV (6.05 eV), and 0.39 eV (1.37 eV), respectively." We also modified Figure 1g as below.
(2) Figure. 1f seems too complicated, so it makes hard to figure out the data and explanation on the configuration of KPFM measurement. Figure 1f to facilitate a better understanding of the KPFM analysis results for the BP/ReS 2 heterojunction.

ANS: We modified
(3) In the manuscript, experimental method on ternary inverter fabrication is not well-described. I suggest to add more explanation on the fabrication process and related experimental details.

ANS:
As the reviewer suggested, we explained the fabrication process flow of the ternary inverter in the "experimental methods" s ction as below: "Fabrication of the ternary inverter. By using a mechanical transfer method, a ReS 2 flake was stacked onto the BP flake, which was exfoliated onto a 90 nm thick SiO 2 /Si substrate. The metal electrode regions were defined using a conventional photolithography process. Finally, Ti/Pd (10/30 nm) layers were deposited by e-beam evaporation to form the contacts for BP and ReS 2 , followed by a lift-off process in acetone. The BP/ReS 2 NDR and the BP TFT devices were designed to function as a driver and a load resistor for a ternary inverter, respectively. The voltage of V DD was applied to the source electrode of the BP TFT, and the source electrode of the BP/ReS 2 NDR device was connected to the ground (V SS ). The common back gate of the BP TFT and BP/ReS 2 NDR devices served as the input voltage (V IN ) electrode. The output voltage (V OUT ) was measured at the drain electrode of the BP/ReS 2 NDR device."

Reviewer: 3 Comments to the Author
We would like to thank you for reviewing our paper; we appreciate your insightful comments on our research. We have revised the manuscript according to your suggestions and believe that the revisions have improved the paper.
Please find below our responses (in blue) to each specific comment (in black) provided by the reviewer. In addition, revisions to the original article are highlighted in red.
The manuscript presents an interesting study of negative differential resistance in black phosphorus/ReS 2 heterojunction, and a demonstration of a multi-value logic (MVL) circuitry using one of the semiconductors as a transistor loaded by the tunnel diode. The material system chosen for this study is indeed new (Ref 5 reported a black phosphorus/SnSe 2 tunnel diode with lower peakto-valley-ratio); and the degree of NDR is improved from this earlier report. The MVL is old in traditional semiconductors, and is similar to the one reported in Ref 7. The results are indicative of heterojunction formation and interband tunneling; the models reported are able to explain the observed experimental work and are similar to prior (cited) work, and are not newly developed for this work.

ANS:
To realize MVL circuits with traditional semiconductor (Si or III-V) devices, considerable number of devices were required (more than nine transistors or four RTDs were needed for ternary logic circuits) R.1-3 . Therefore, this kind of MVL circuit consisting of conventional CMOS devices or RTDs, from a practical standpoint, suffered from high power dissipation due to the increased parasitic capacitance of the interconnects.
In this work, we proposed a new approach to realize a ternary inverter for MVL, where a BP/ReS 2 heterojunction-based NDR device and a built-in BP p-channel TFT were integrated. This approach, which is based on NDR devices, is expected to fulfil low-power advantages of future MVL circuits by reducing the parasitic interconnect capacitance.

Sign-change in output-conductance (∂I D /∂V D )
Si n-chan in t anscon ctanc Firstly, because our BP/ReS 2 heterojunction was formed by a broken-gap band alignment, this type-III junction-based NDR device is independent of the thickness of the flakes. However, in the case of a WSe 2 /MoS 2 heterojunction device (Ref. 7), which was formed by a staggered-gap band alignment, NDR behavior was only observed under specific conditions (2 nm WSe 2 /10 nm MoS 2 ).
Secondly, only the tunneling mechanism was considered in the analytic model of Ref. 7. However, to investigate the carrier transport mechanism of our NDR device, we developed a new analytic model that considers both tunneling/diffusion currents and parasitic series resistance, which could help elucidate the peak-/valley-currents and voltages of the NDR device, respectively.
Lastly, the ternary inverters in our work and Ref. 7 operated differently. In our work, a sign-change in output-conductance (∂I D /∂V D ) was used, and in Ref. 7, a sign-change in transconductance (∂I D /∂V G ) was used. This is evidence that we proposed a totally different method to demonstrate MVL circuits.
as on th vi w 's comm nts, w 'v added and modified the following sentences in the article.
"In addition, as an MVL application, we present a ternary inverter (having three states) that combines a BP/ReS 2 heterojunction NDR device and a BP p-channel thin film transistor (TFT). This integration approach based on NDR devices is expected to fulfil low-power advantages of future MVL circuits by reducing the parasitic interconnect capacitance. In particular, compared to a type-II heterojunction, a type-III heterojunction can easily implement a highly doped n + /p + heterojunction without a separate process, such as electrostatic doping by gate bias and a chemical doping process." "Furthermore, through temperature-dependent current-voltage (I-V) measurements and the proposed analytic NDR device model, where tunneling/diffusion currents and parasitic series resistance were considered simultaneously, we quantitatively study the temperature-dependent device operations." The work is of high interest, and shows the richness of 2D layered material system choices. It improves on prior work (which is very important), the experiments and models presented here do not represent a new finding.
Some of the claims in the manuscript could be misleading and should be corrected in future versions:

ANS:
The authors think that this work has three critical points (i.e., new findings).
i) Doping-free fabrication process using a type-III heterojunction: The BP/ReS 2 heterojunction was formed by a broken-gap band alignment. Subsequently, based on the broken-gap band alignment (type-III heterojunction), a highly doped n + /p + heterojunction was easily implemented without using a separate doping process, such as electrostatic doping by gate bias or chemical doping, which is generally required in a type-II heterojunction to realize an NDR device.
ii) Quantitative analysis through development of an analytic NDR device model: The carrier transport mechanism of the BP/ReS 2 heterojunction NDR device was investigated in detail at various temperatures between 180 K and 300 K with the developed analytic NDR device model, simultaneously considering both tunneling/diffusion currents and parasitic series resistance.
iii) New implementation of a ternary inverter: As an MVL application expected to satisfy future low-power demands by reducing the parasitic capacitance of the interconnects, a ternary inverter could be fabricated by integrating the BP/ReS 2 heterojunction NDR device as a driver with the built-in BP p-channel TFT as a load resistor, where the total resistance in the BP TFT was controlled by an applied gate voltage.
(1) In the introduction (page 4), it is claimed that "most NDR devices have shown very low PVCR at low temperatures... heterojunctions interfaces suffered significantly from defects...". This is incorrect. SiGe and III-V heterojunctions show robust, very high PVCRs at room temperature, much higher and more reproducible than what is reported in this manuscript and most 2D layered materials. Many of them are used in commercial devices, for example broken-gap III-V backward diodes are used for millimeter wave imaging applications. MVL logic has been demonstrated with 3D tunnel junctions, it just has not been very useful.
These sorts of claims should be carefully considered because sometimes the 2D materials community do not do proper research of existing 3D semiconductor capabilities and make erroneous claims.

ANS:
We agree with the reviewer comment that NDR devices based on SiGe or III-V heterojunctions exhibited reproducible NDR behavior with high PVCR values (above 10) at room temperature. We corrected this in the article as below.
However, it is still true that the formation of various types of heterojunctions (type-I, II, and III) on SiGe and III-V materials is limited by threading dislocations, which are normally caused at the junction interface by lattice mismatch during film growth. Although the threading dislocation that increases the valley current of the NDR device can be reduced through superlattice and nanowire structures, it is hard to avoid that the fabrication process becomes more complex.
Whereas, various high-quality heterojunctions can be formed without the lattice mismatch issue by just stacking 2D materials due to the absence of dangling bonds on their surface (The authors believe that this is the most important advantage of 2D semiconductor materials compared to conventional 3D materials).
In order to clarify this, we modified and added the following sentences in the article.
"However, at the current stage of research, most NDR devices have shown very low peak-to-valley current ratio (PVCR), which is an important parameter for evaluating NDR device performance, and the NDR property was normally observed at low temperatures 6,8,18,20,21,23 . Furthermore, because most of the Esaki diodes and RTDs were fabricated in Si-Ge and III-V semiconductors [2][3][4][8][9][10][11][12][13][14] , the formation of various types of heterojunctions (type-I, II, and III) is limited by threading dislocations, which are normally caused at the junction interface by lattice mismatch during film growth. the heterojunction interfaces suffered significantly from defects, such as dislocation by lattice mismatch. These imperfections at the interface degrade the NDR device performance as the carriers are trapped and recombined at the defect sites. Although the threading dislocation that increases the valley current of the NDR device can be reduced by applying superlattice and nanowire structures, it is hard to avoid that the fabrication process becomes mo compl x." " Fig. 2b shows the current-voltage (I-V) characteristic of the NDR device on a linear scale. Here, the NDR behavior was observed between 0.4 V and 0.9 V with a PVCR of 4.2, which is the highest value in previously reported NDR devices based on 2D materials [5][6][7]18,19 and is also comparable to the values for other NDR devices fabricated on conventional 3D semiconductors, such as Si, Ge, and III-V compound semiconductors 2,3,8,10-12 ." (2) In page 4, the claim of " ... electrostatic doping ... " is incorrect. Any useful electronic device will need to be doped to be controlled; it does not help in adjusting threshold voltages etc if the doping is left to nature. This claim is repeated in page 6. This is a fundamental underestimation of the importance of doping in device physics.

ANS:
What we wanted to say in this sentence is that a highly doped n + /p + tunnel heterojunction can be implemented without using any doping process (electrostatic doping by gate bias, chemical doping process, etc.). This does not mean that the doping process is not important in device physics, but rather that the fabrication process for the tunnel heterojunction of the NDR device becomes very simple. As already mentioned, the highly doped n + /p + tunnel heterojunction could easily be implemented by forming a type-III broken-gap band alignment.
(3) Because the thickness of the BP layer is so high, how is the gating affecting the conductance? If it is changing the conductivity of the entire channel, it should reach in and also affect the band alignments, etc. This is not included in the analysis or model.

ANS:
Because of the large thickness of the BP layer, the top region of the BP film is expected to be weakly modulated by gate bias (FYI, this top BP region faces ReS 2 to form the type-III junction). If the conductivity of the top BP region is unaffected by gate bias, the drain current of the BP TFT (the solid line in the figure below) will be probably unchanged (or only slightly changed) as a function of gate voltage (like the red dashed line) because the current flowing through the BP bulk region dominates the drain current at the off-state. For reference, the deterioration of the on/off-current ratio in BP TFTs with increasing BP film thickness was also reported R.4 .
As shown in the figure below, we modified the analytic NDR device model by considering the Fermi level modulation via the gating effect. However, it was hard to accurately anticipate the gate e-field effect on the top region in the BP film due to the screening effect of the bottom region. Thus, as shown below, we estimated the gating effect in the BP/ReS 2 NDR device by assuming that the Fermi level of the BP region shifts downward by 0.1 eV with decreasing gate voltage, from 30 V to -30 V, in the analytic model (0.1 eV per 60 V = 0.00167 eV/V).
In order to clarify this, we added the following sentence in the article.
"Th ction o peak-current in BP/ReS 2 NDR devices with decreasing gate voltage could also be estimated using the I D -V D curves calculated by the analytic mo l (S ppo tin In o mation Fi . S5)." We also modified Supporting Information Figure S5 and added the related sentences.
In the figure caption: "(b) Theoretically calculated I D -V D curves of the BP/ReS 2 NDR device as gate voltage decreases from 30 V to -30 V." In the Supporting Information: "As shown in Figure S5b, the reduction of peak-current in BP/ReS 2 NDR devices with decreasing gate voltage could also be estimated using the I D -V D curves calculated by the analytic model. In the