Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio

Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10−14 A, leading to ultrahigh on/off ratio over 109, about ∼103 times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics.


Supplementary Note 1  Electrostatic potential simulation at different states
Geometry and material parameters of the simulation model are given as Supplementary Figure   5, Supplementary Tables 1 and Supplementary Table 2. Typical channel length of our device is about 2 μm. In fact, we performed two simulations for two channel lengths: 30 nm and 2 μm.
The potential distribution in both channel lengths is almost similar (Figure 2 and Supplementary Figure S6). Potential distribution of 2 μm channel cannot illustrate in single image due to large difference between channel length and thickness (2000/7 nm). Therefore, we used simulation model with the channel length of 30 nm for better eye capturing. In this small difference between channel length and thickness (30/7 nm), electrostatic potential distribution can illustrate in single image.
The floating gate potential V FG estimated by Cappelletti 1 is: where Q FG is the charge stored in the floating gate, C C , C S , C D , and C B are the capacitances between FG and control gate, source, drain and semiconductor channel, respectively, and C T is the total capacitance ( . V C , V S , V D , and V B are the potentials of control gate, drain, source, and semiconductor channel, respectively.
Our device has no control gate, and the source is connected to the ground, which leads to zero for V C and V S . Therefore, the Supplementary Equation 1 becomes: The capacitance is defined to: where ε r is relative permittivity, ε 0 is absolute permittivity, A is capacitor area, and d is thickness of insulator. All parameters of ε r , ε 0 , and d are the same in C S , C D , and C B . Capacitance of the drain electrode C D is in general very small compared to channel capacitance due to small contact area and therefore, C D /C T is small and the potential of the floating gate is nearly zero if no charge is accumulated in the floating gate. In our device, the area of contact electrode is not negligible due to relatively large pattern area of the drain contact. We have measured overlapped areas between graphene -metal electrodes (drain or source) and graphene -MoS 2 from the optical images (Supplementary Figures 2, 14) which were same areas, it leads to: By inserting equation (4) into equation (2), V FG can be obtained as: At the programing state (Fig. 2a) Table 2).
Electrostatic potential and electric field simulation were performed with those V FG (Figure 2 and Supplementary Figure 8). Asymmetric potential of 2.2 V at FG/source and 3.8 V at FG/drain were formed at the programing and erasing states, which allows asymmetric charge tunneling at the drain electrode to FG.

Supplementary Note 2  Fundamental difference between Flash and TRAM
To understand the fundamental difference in mechanism of our TRAM and Flash, we

Supplementary Note 3  Carrier concentration calculation
We calculate the carrier concentration of MoS 2 in on state based on the on current level in Fig. 1e Drift current density can be calculated by equation: Where, J is the current density, q is charge of the electron, E is the electric field between source and drain, µn and µp are the mobility of electron and hole, respectively. Carrier concentration can be calculated by: Where, I is the current, l, w are the channel length and channel width, respectively.
To calculate the mobility, we use the equation: Moreover, our TRAM achieved high stretchability over 19% strain due to absence of thick and rigid blocking-oxide and control-gate electrode (Figure 7), while three terminal memory cannot demonstrate stretchability due to the rigid and thick blocking oxide.