Single crystal functional oxides on silicon

Single-crystalline thin films of complex oxides show a rich variety of functional properties such as ferroelectricity, piezoelectricity, ferro and antiferromagnetism and so on that have the potential for completely new electronic applications. Direct synthesis of such oxides on silicon remains challenging because of the fundamental crystal chemistry and mechanical incompatibility of dissimilar interfaces. Here we report integration of thin (down to one unit cell) single crystalline, complex oxide films onto silicon substrates, by epitaxial transfer at room temperature. In a field-effect transistor using a transferred lead zirconate titanate layer as the gate insulator, we demonstrate direct reversible control of the semiconductor channel charge with polarization state. These results represent the realization of long pursued but yet to be demonstrated single-crystal functional oxides on-demand on silicon.


Supplementary Note 1: Materials growth by pulsed laser deposition (PLD)
STO/LSMO20/PZT: 20 nm of LSMO is grown on the STO (001) substrate at 750 °C with repetition rate of 2 Hz. The film is cooled down to 630°C at a rate of 5°C /min. PZT is grown at this temperature using 10 HZ repetition rate. Both the layers are grown at the oxygen background pressure of 100 mTorr and laser energy density of 1 J/cm 2 . The film is cooled down to room temperature at the rate of 5°C /min in 1 atm pressure of oxygen. Supplementary Figure 1a  substrate, the film is cooled down to 700 °C (cooling rate 5 °C/min) where 15 nm of SRO is grown at 10 HZ. Then the film is cooled down to 630 °C where 60 nm of PZT is grown. After the PZT growth 15 nm of SRO is grown at same temperature. All the layers are grown at the oxygen background pressure of 100 mTorr and laser energy density of 1 J/cm 2 . The film is cooled down to room temperature at the rate of 5 °C/min in 1 atm pressure of oxygen.
DSO/LSMO20/BTO: 20 nm LSMO is grown following the same recipe as described earlier. Then the film is cooled down to 600 °C at a rate of 10 °C/min and BTO is grown at that temperature. The oxygen background pressure is 20 mTorr, laser energy density is 1.5 J/cm 2 and repetition rate is 10 Hz. The film is cooled down to room temperature at the rate of 10 °C /min in 1 atm pressure of oxygen.
Superlattices: Superlattices of SrTiO3/CaTiO3 were synthesized using Reflection High Energy Electron Diffraction (RHEED) -assisted PLD. To ensure stoichiometric transfer of STO and CTO, growth temperature was set at 700 C and growth pressure was 50 mTorr with both targets being ablated by a laser fluence of 1.5 J/cm 2 . The growth was monitored using RHEED with Frank-van der Merwe layer-by-layer growth mode present throughout the process.
DyScO3/SrRuO340/BiFeO370/CoFeB4/Pt4: These films were prepared on single-crystalline (110) DyScO3 substrates by PLD. For SRO and BFO films substrate temperatures were 690 °C and 700 °C and Oxygen pressures were 50 mTorr and 100 mTor , respectively. The films were grown at a repetition rate of 8 Hz with a laser fluence of 1.1 J.cm −2 . After growth, the samples were cooled to room temperature in an Oxygen pressure of 750 Torr.

Supplementary Note 2: Details of single crystal FE transfer process
The key to transfer single crystal FE onto Si is using a suitable sacrificial layer which, a) allows the crystalline growth of the FE layer on top of it and b) can be selectively etched away without affecting the ferroelectric layer. Fig. 1 shows the steps involved in the transfer process. We grow single crystal PZT on 20 nm thick LSMO coated STO substrate by using PLD. Then poly methyl methacrylate (PMMA) layer is spin coated, which serves as the transfer stamp. We chose PMMA over other typical stamps such as PDMS, since the adhesion between PZT and PMMA is better than that between PZT and PDMS. Moreover, PMMA can be easily and cleanly removed by organic chemical such as acetone which helps to get better yield in transferring nano materials (1). PMMA 950A4 is spin coated at 4000 rpm for 30 seconds, followed by a baking at 120 °C for 1 minute, which leaves a uniform film of 200-250 nm thickness. The second and the most important task to successfully transfer single crystal PZT is finding an etchant which removes only the sacrificial layer LSMO and does not react with the PMMA stamp and PZT. We use KI (4 mg) + HCl (5 mL) + H2O (200 mL) for etching (2). Since LSMO/PZT stack is covered by PMMA stamp, LSMO is slowly etched away only from the side. The possible chemical reaction between LSMO and the etchant is: La0.7Sr0.3MnO3+H2O+5 HCl+ KI = MnCl2 + Cl2 + ½ I2 + KOH + 3 H2O + La0.7Sr0.3Cl After 12 hours, PZT/PMMA stack is released and collected from the solution. Then we wash it by DI water and dry up by N2 gas. The stamp is transferred by using micromanipulator and a gentle force on the target substrate, followed by removal of PMMA by acetone. Following this procedure we have transferred various thickness of ~200nm. Thermal oxidation is used to thin the SOI layer down to ~100nm. The active area is patterned by optical lithography followed by dry etching. A sacrificial thermal oxide (~3nm) is grown to reduce the etch damage. After using diluted HF to remove the sacrificial oxide, a 3nm gate thermal oxide was grown immediately. The channel region is patterned by optical lithography, and then ion implantation is performed to dope the source/drain regions n-type (5×10 15 As + /cm 2 at 80keV, 7° tilt). Rapid thermal annealing (20s @ 900 °C in N2) is used to activate the dopants. Forming gas annealing (25 minutes @ 350 °C) was performed to improve Si/SiO2 interface properties. Then PZT with the stamp is transferred on the channel region. The PMMA is washed away by acetone, leaving PZT on the channel region. Subsequently gate electrode patterning by optical lithography and Au deposition by thermal evaporation were done.
Supplementary Figure 10 shows the optical image of a typical transistor. We fabricated a number of transistors and in this Supplementary section we show the results of a transistor different than the main text's one. Supplementary Figure 11a shows the ID-VG (top gate) at VG (back gate) =-4V at different VD.
Note that the ON current increases with increasing VD. All the curves show anti-clock wise hysteresis. The shape of the loop can be understood by noting the following: When the transistor is ON, the ferroelectric is essentially between two metal plates. Therefore, the switching of the polarization happens just it does in a usual capacitor structure and a reasonably sharp transition is seen when the transistor channel turns OFF.
On the other hand, starting from OFF, the ferroelectric is between a metal plate (top electrode) and an insulator. The insulator slowly turns into a metal as the voltage across it is increased. Therefore, the actual voltage drop across the ferroelectric varies non-linearly as the total gate voltage is increased. Hence the transition from OFF to ON stretches out and shows a slower transition from OFF to ON than from ON to OFF. When top gate is grounded and only back gate voltage is swept, no hysteresis is seen in the ID-VG (see Supplementary Figure 11b) indicating that the observed hysteresis for the top gate sweep indeed comes from the ferroelectric polarization.
Supplementary Figure 12 shows ID-VG (top gate) characteristics of a different sample where two different ID-VG sweeps were performed with a time gap of 1 day. The two measurements show identical behavior, indicating that the polarization retention is robust and its effect on the Si channel is repeatable.