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Three-dimensional integration of nanotechnologies for computing and data storage on a single chip

Nature volume 547, pages 7478 (06 July 2017) | Download Citation


The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors—promising new nanotechnologies for use in energy-efficient digital logic circuits1,2,3 and for dense data storage4—fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce ‘highly processed’ information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems5.

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We acknowledge the support of NSF (CNS-1059020), DARPA (W909MY-16-1-0001), STARnet SONIC, member companies of the Stanford SystemX Alliance, and the Hertz Fellowship and Stanford Graduate Fellowship for M.M.S. We are grateful to C. Gupta for discussions.

Author information


  1. Department of Electrical Engineering, Stanford University, Stanford, California, USA

    • Max M. Shulaker
    • , Gage Hills
    • , Rebecca S. Park
    • , Roger T. Howe
    • , Krishna Saraswat
    • , H.-S. Philip Wong
    •  & Subhasish Mitra
  2. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts, USA.

    • Max M. Shulaker
  3. Department of Computer Science, Stanford University, Stanford, California, USA

    • Subhasish Mitra


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M.M.S. led and was involved in all aspects of the project, and performed all of the design, layout, fabrication and testing. G.H. contributed to the design and testing. R.S.P., R.T.H. and K.S. contributed to the design of the silicon transistors. H.-S.P.W. and S.M. were in charge and advised on all parts of the project.

Competing interests

The authors declare no competing financial interests.

Corresponding author

Correspondence to Max M. Shulaker.

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