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Three-dimensional integration of nanotechnologies for computing and data storage on a single chip


The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors—promising new nanotechnologies for use in energy-efficient digital logic circuits1,2,3 and for dense data storage4—fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce ‘highly processed’ information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems5.

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Figure 1: Our 3D nanosystem.
Figure 2: Illustration, schematic and operation of our nanosystem.
Figure 3: Characterization of the components of our nanosystem.
Figure 4: Results from our nanosystem.

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We acknowledge the support of NSF (CNS-1059020), DARPA (W909MY-16-1-0001), STARnet SONIC, member companies of the Stanford SystemX Alliance, and the Hertz Fellowship and Stanford Graduate Fellowship for M.M.S. We are grateful to C. Gupta for discussions.

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Authors and Affiliations



M.M.S. led and was involved in all aspects of the project, and performed all of the design, layout, fabrication and testing. G.H. contributed to the design and testing. R.S.P., R.T.H. and K.S. contributed to the design of the silicon transistors. H.-S.P.W. and S.M. were in charge and advised on all parts of the project.

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Correspondence to Max M. Shulaker.

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Extended data figures and tables

Extended Data Figure 1 Fabrication flow for our nanosystem.

See Methods section ‘Fabrication’ for details.

Extended Data Figure 2 Schematic of the CNFET-based classification accelerator.

The combinational logic is implemented with CNFETs (on the second layer), whereas the registers are implemented with silicon FETs (on the first layer). H.A., half-adder; clk, clock; D, latch input; Q, latch output.

Extended Data Figure 3 Small-scale example of how the CNFET-based classification accelerator performs classification.

F.V., feature vector.

Extended Data Figure 4 Measured waveform of the CNFET-based classification, testing all possible combinations.

Extended Data Figure 5 Implementation of the CNFET inverter operating as a gas sensor.

The resistance of the sensor Rsensor depends on the ambient air and VGS (Rsensor = f(ambient, VGS)), whereas the resistance of the pull-down CNFET Rpull-down depends only of VGS (Rpull-down = f(VGS)).

Extended Data Figure 6 Input (‘in’) and output voltage Vout (‘out’) of the CNFET inverter (gas and vapour sensor) after non-covalent functionalization of the pull-up CNFET and oxide deposition over the pull-down CNFET.

Extended Data Figure 7 CNFET gas sensors.

a, Characterization of the CNFET gas sensors. Sample size is 90 (30 of each the three types of CNFET gas sensor). ΔR is defined as the resistance measured after exposure to the given gas divided by the baseline resistance in vacuum, with the resistance is both cases measured at VGS = −3 V and VDS = −2 V (error bars show 95% confidence intervals). b, Example layout showing how sub-arrays of the complete chip can be functionalized. By measuring the percentage of RRAM cells that are set to 1 in each sub-array during the sensing phase of operation, an average value for the CNFET sensing circuit can be calculated, which corresponds to Rsensor.

Extended Data Figure 8 Characterization of the CNFET gas sensors.

a, Sensor response is reversible, responding and returning to steady-state within approximately 45 s. b, Sensor response is robust: 30 repeated measurements of the current–voltage curve (‘IVs’) from the same CNFET gas sensor yield similar responses. c, The techniques that we used to realize VLSI-compatible CNFET logic simultaneously improve CNFET sensor performance. The CNFET with purely semiconducting CNTs (‘Semiconducting’) has a much larger sensitivity and change in its response than a CNFET with metallic CNTs (‘Metallic’), as indicated by the arrows.

Extended Data Figure 9 Aligned active layouts are used to overcome variability in CNTs.

VDD, supply voltage; GND, ground; OUT, output node.

Extended Data Figure 10 Test chamber for our nanosystem.

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Shulaker, M., Hills, G., Park, R. et al. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547, 74–78 (2017).

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