Extended Data Figure 2 : Schematic of the CNFET-based classification accelerator.

From: Three-dimensional integration of nanotechnologies for computing and data storage on a single chip

Extended Data Figure 2

The combinational logic is implemented with CNFETs (on the second layer), whereas the registers are implemented with silicon FETs (on the first layer). H.A., half-adder; clk, clock; D, latch input; Q, latch output.