Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome1,2,3 by using optical communications based on chip-scale electronic–photonic systems4,5,6,7 enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic–photonic chips9,10,11 are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic–photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics12, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors13,14,15,16. This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

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We thank S. Twigg, Q. Nguyen, and M. Moreto Planas for help with processor infrastructure, A. Srinivasan for help with photodetector characterization, and S. Han for help with chip photos. This work was supported by DARPA POEM award HR0011-11-C-0100, led by J. Shah and DARPA PERFECT award HR0011-12-2-0016, led by J. Cross. We thank M. Casper, J. Torneden, and the team at the Kansas City Plant for their support of our design submissions over the years leading up to this work. Support is also acknowledged from the Berkeley Wireless Research Center, UC Berkeley ASPIRE Lab, MIT CICS, National Science Foundation, FCRP IFC, Trusted Foundry, Intel, Santec, and NSERC. The views expressed are those of the authors and do not reflect the official policy or position of the DoD or the US Government.

Author information

Author notes

    • Jason S. Orcutt
    •  & Jeffrey M. Shainline

    Present addresses: IBM T. J. Watson Research Center, Yorktown Heights, New York 10598, USA (J.S.O.); National Institute for Standards and Technology, Boulder, Colorado 80305, USA (J.M.S.).

    • Chen Sun
    • , Mark T. Wade
    • , Yunsup Lee
    •  & Jason S. Orcutt

    These authors contributed equally to this work.


  1. University of California, Berkeley, Berkeley, California 94720, USA

    • Chen Sun
    • , Yunsup Lee
    • , Andrew S. Waterman
    • , Rimas R. Avizienis
    • , Sen Lin
    • , Henry M. Cook
    • , Albert J. Ou
    • , Krste Asanović
    •  & Vladimir M. Stojanović
  2. Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA

    • Chen Sun
    • , Jason S. Orcutt
    • , Luca Alloatti
    • , Michael S. Georgas
    • , Benjamin R. Moss
    • , Amir H. Atabaki
    • , Jonathan C. Leu
    • , Yu-Hsin Chen
    •  & Rajeev J. Ram
  3. University of Colorado, Boulder, Boulder, Colorado 80309, USA

    • Mark T. Wade
    • , Jeffrey M. Shainline
    • , Rajesh Kumar
    • , Fabio Pavanello
    •  & Miloš A. Popović


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C.S. developed the thermal tuning circuitry, designed the memory bank, implemented the ‘glue-logic’ between various electronic components, and performed top-level assembly of electronics and photonics. M.T.W. optimized modulator designs for thermal tuning, designed the grating couplers, and performed top-level assembly of photonics regions used in our demonstration. C.S. and Y.L. designed the system-level architecture and demonstrated the processor with photonic input/output. Y.L. wrote and/or adapted the test programs for the processor demonstration. Y.L. and A.S.W. developed the RISC-V ISA and processor implementation. J.S.O. created the CAD infrastructure for photonic layouts, designed the photodetector used in our demonstration, and assembled initial photonic layouts and passive devices. L.A. improved the CAD infrastructure, developed new rules for design rule checking, and contributed new photodetector designs. C.S., M.T.W., Y.L., and L.A. contributed to chip verification and testing. M.S.G. designed and implemented the receiver circuit. J.M.S. designed, implemented, and tested the original version of the modulator. R.R.A. performed the physical implementation of the processor and designed the chip and adapter printed circuit boards. S.L. developed the selective substrate removal process and contributed to the thermal tuning method. B.R.M. assisted with chip implementation and performed initial substrate removal experiments. R.K. assisted in the rework of new grating coupler designs. F.P. contributed to layout and analysis for couplers and modulators. A.H.A. created new photodetector designs. H.M.C. and A.J.O. assisted with processor design. J.C.L. and Y.-H.C. contributed components in the transceiver regions. V.M.S., M.A.P., R.J.R., and K.A. supervised the project.

Competing interests

C.S., M.T.W., R.J.R., M.A.P., and V.M.S. are developing silicon photonic technologies at Ayar Labs, Inc. Y.L., A.S.W., and K.A. are working on RISC-V ISA platforms at SiFive Inc. J.S.O. is now employed at IBM developing silicon photonics technologies.

Corresponding authors

Correspondence to Krste Asanović or Rajeev J. Ram or Miloš A. Popović or Vladimir M. Stojanović.

Extended data

Supplementary information


  1. 1.

    Processor Demonstration Video

    An animated overview of the chip (starts at 0:05) and description of the test setup for the optical memory (starts at 0:59). The demonstration of the processor running programs starts at 2:36, with temperature changing events applied starting at 5:46, with and without the thermal tuning circuit enabled. This uploaded version is the 480p quality version, sized to be just under 30MB to not exceed the individual file size limit for supplementary information. We would like to point any readers to the full-quality 1080p version, accessible to only those with the following link: https://drive.google.com/file/d/0Bw4D2gUSMil1T3VrcVpybzh5dDg/view?usp=sharing

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