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A two-qubit logic gate in silicon


Quantum computation requires qubits that can be coupled in a scalable manner, together with universal and high-fidelity one- and two-qubit logic gates1,2. Many physical realizations of qubits exist, including single photons3, trapped ions4, superconducting circuits5, single defects or atoms in diamond6,7 and silicon8, and semiconductor quantum dots9, with single-qubit fidelities that exceed the stringent thresholds required for fault-tolerant quantum computing10. Despite this, high-fidelity two-qubit gates in the solid state that can be manufactured using standard lithographic techniques have so far been limited to superconducting qubits5, owing to the difficulties of coupling qubits and dephasing in semiconductor systems11,12,13. Here we present a two-qubit logic gate, which uses single spins in isotopically enriched silicon14 and is realized by performing single- and two-qubit operations in a quantum dot system using the exchange interaction, as envisaged in the Loss–DiVincenzo proposal2. We realize CNOT gates via controlled-phase operations combined with single-qubit operations. Direct gate-voltage control provides single-qubit addressability, together with a switchable exchange interaction that is used in the two-qubit controlled-phase gate. By independently reading out both qubits, we measure clear anticorrelations in the two-spin probabilities of the CNOT gate.

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Figure 1: Silicon two-qubit logic device, incorporating SET read-out and selective qubit control.
Figure 2: Exchange spin funnel.
Figure 3: Controlled phase (CZ) gate operation time.
Figure 4: Two-spin correlations for a two-qubit logic gate.


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We thank S. Bartlett for discussions and C. M. Cheng for contributions to the preparation of the experimental setup. We acknowledge support from the Australian Research Council (CE11E0001017), the US Army Research Office (W911NF-13-1-0024) and the NSW Node of the Australian National Fabrication Facility. M.V. acknowledges support from the Netherlands Organization for Scientific Research (NWO) through a Rubicon Grant. The work at Keio was supported in part by the Grant-in-Aid for Scientific Research by MEXT, in part by NanoQuine, in part by FIRST and in part by the JSPS Core-to-Core Program.

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Authors and Affiliations



M.V., C.H.Y. and J.C.C.H. performed the experiments. M.V. and F.E.H. fabricated the devices. K.M.I. prepared and supplied the 28Si epilayer wafer. W.H., J.P.D., J.T.M., S.S and A.L. contributed to the preparation of the experiments. M.V., C.H.Y., A.M. and A.S.D. designed the experiment and discussed the results. M.V. analysed the results. M.V. and A.S.D. wrote the manuscript with input from all co-authors.

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Correspondence to M. Veldhorst or A. S. Dzurak.

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The authors declare no competing financial interests.

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Veldhorst, M., Yang, C., Hwang, J. et al. A two-qubit logic gate in silicon. Nature 526, 410–414 (2015).

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