An indispensable part of our personal and working lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the past fifty years. Such Moore scaling now requires ever-increasing efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and increase our understanding of integrated-circuit scaling, here I review fundamental limits to computation in the areas of manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, I recapitulate how some limits were circumvented, and compare loose and tight limits. Engineering difficulties encountered by emerging technologies may indicate yet unknown limits.
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Cavin, R. K., Lugli, P. & Zhirnov, V. V. Science and engineering beyond Moore’s law. Proc. IEEE 100, 1720–1749 (2012)This paper reviews the historical effects and benefits of Moore’s law, discusses challenges to further growth, and offers several strategies to maintain progress in electronics.
Chien, A. A. & Karamcheti, V. Moore’s law: the first ending and a new beginning. IEEE Computer 46, 48–53 (2013)
Herken, R. (ed.) The Universal Turing Machine: A Half-Century Survey 2nd edn (Springer, 2013)
Andreesen, M. Why software is eating the world. The Wall Street Journal http://online.wsj.com/news/articles/SB10001424053111903480904576512250915629460 (August 2011)
Padua D. A., ed. Encyclopedia of Parallel Computing (Springer, 2011)
Shaw, D. E. Anton: a special-purpose machine that achieves a hundred-fold speedup in biomolecular simulations. In Proc. Int. Symp. on High Performance Distributed Computing 129–130 (IEEE, 2013)
Hameed, R. et al. Understanding sources of inefficiency in general-purpose chips. Commun. ACM 54, 85–93 (2011)
Cong, J., Reinman, G., Bui, A. T. & Sarkar, V. Customizable domain-specific computing. IEEE Des. Test Comput. 28, 6–15 (2011)
Mernik, M., Heering, J. & Sloane, A. M. When and how to develop domain-specific languages. ACM Comput. Surv. 37, 316–344 (2005)
Olukotun, K. Beyond parallel programming with domain specific languages. In Proc. Symp. on Principles and Practice of Parallel Programming 179180 (ACM, 2014)
Aaronson, S. & Shi, Y. Quantum lower bounds for the collision and the element distinctness problems. J. ACM 51, 595–605 (2004)
Jain, R., Ji, Z., Upadhyay, S. & Watrous, J. QIP = PSPACE. Commun. ACM 53, 102–109 (2010)
Nielsen, M. A. & Chuang, I. L. Quantum Computation and Quantum Information (Cambridge Univ. Press, 2011)
International Technology Roadmap for Semiconductors (ITRS). http://www.itrs.net/ (2013)Documents available at this website describe in detail the current state of the art in integrated circuits and near-term milestones.
Sylvester, D. & Keutzer, K. A global wiring paradigm for deep submicron design. IEEE Trans. CAD 19, 242–252 (2000)
A Quantum Information Science and Technology Roadmap Los Alamos Technical Report LA-UR-04–1778, http://qist.lanl.gov (2004)
Meindl, J. Low power microelectronics: retrospective and prospect. Proc. IEEE 83, 619–635 (1995)
Davis, J. A. et al. Interconnect limits on gigascale integration (GSI) in the 21st Century. Proc. IEEE 89, 305–324 (2001)This paper discusses physical limits to scaling interconnects in integrated circuits, classifying them into fundamental, material, device, circuit and system limits.
Ma, X. & Arce, G. R. Computational Lithography (Wiley, 2011)
Mazzola, L. Commercializing nanotechnology. Nature Biotechnol. 21, 1137–1143 (2003)
Moore, G. E. Cramming more components onto integrated circuits. Electronics 38, 1–4 (1965)
Bohr, M. Interconnect scaling—the real limiter to high performance ULSI. In Proc. Int. Elec. Device Meeting 241–244 (IEEE, 1995)This paper explains why wires, rather than gates, have become the main limiter to the performance of ultra-large integrated circuits.
Shelar, R. & Patyra, M. Impact of local interconnects on timing and power in a high performance microprocessor. IEEE Trans. CAD 32, 1623–1627 (2013)
Almeida, V. R., Barrios, C. A., Panepucci, R. R. & Lipson, M. All-optical control of light on a silicon chip. Nature 431, 1081–1084 (2004)
Chang, M.-C. F., Roychowdhury, V. P., Zhang, L., Shin, H. & Qian, Y. RF/wireless interconnect for inter-and intra-chip communications. Proc. IEEE 89, 455–466 (2002)
Hisamoto, D. et al. FinFET—a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron. Dev. 47, 2320–2325 (2002)
Seabaugh, A. The tunneling transistor. IEEE Spectrum http://spectrum.ieee.org/semiconductors/devices/the-tunneling-transistor (2013)
Ozdal, M. M., Burns, S. M. & Hu, J. Algorithms for gate sizing and device parameter selection for high-performance designs. IEEE Trans. CAD 31, 1558–1571 (2012)
Rutenbar, R. A. Design automation for analog: the next generation of tool challenges. In Proc. Int. Conf. Computer-Aided Design of Integrated Circuits 458–460 (IEEE, 2006)
Rutenbar, R. A. Analog layout synthesis: what’s missing? In Proc. Int. Symp. Physical Design of Integrated Circuits 43 (ACM, 2010)
Ho, R., Mai, K., Kapadia, H. & Horowitz, M. Interconnect scaling implications for CAD. In Proc. Int. Conf. Computer-Aided Design of Integrated Circuits 425–429 (IEEE, 1999)
Markov, I. L., Hu, J. & Kim, M.-C. Progress and challenges in VLSI placement research. In Proc. Int. Conf. Computer-Aided Design of Integrated Circuits 275–282 (IEEE, 2012)
Puri, R. Opportunities and challenges for high-performance CPU designs and design automation. In Proc. Int. Symp. Physical Design of Integrated Circuits 179 (ACM, 2013)
Lavagno, L., Martin, G. & Scheffer, L. Electronic Design Automation for Integrated Circuits Handbook (CRC Press, 2006)
Chinnery, D. G. & Keutzer, K. Closing the Gap Between ASIC and Custom: Tools And Techniques For High-Performance ASIC Design (Springer, 2004)
Chinnery, D. G. & Keutzer, K. Closing the Power Gap between ASIC and Custom: Tools and Techniques for Low Power Design (Springer, 2007)
Sangiovanni-Vincentelli, A. L., Carloni, L. P., De Bernardinis, F. & Sgroi, M. Benefits and challenges for platform-based design. In Proc. Design Automation Conf. 409–414 (ACM, 2004)
Landauer, R. Irreversibility and heat generation in the computing process. IBM J. Res. Develop. 5, 183–191 (1961)
Bérut, A. et al. Experimental verification of Landauer’s principle linking information and thermodynamics. Nature 483, 187–189 (2012)
Bennett, C. H. & Landauer, R. The fundamental limits of computation. Sci. Am. 253, 48–56 (1985)
Aharonov, Y. & Bohm, D. Time in the quantum theory and the uncertainty relation for time and energy. Phys. Rev. 122, 1649–1658 (1961)
Lloyd, S. Ultimate physical limits on computation. Nature 406, 1047–1054 (2000)This paper derives several ab initio limits to computation, points out that modern quantum devices operate close to their energy-efficiency limits, but concludes that resulting large-scale limits are very loose.
Ren, J. & Semenov, V. K. Progress with physically and logically reversible superconducting digital circuits. IEEE Trans. Appl. Supercond. 21, 780–786 (2011)
Monroe, C. et al. Large-scale modular quantum-computer architecture with atomic memory and photonic interconnects. Phys. Rev. A 89, 022317 (2014)
Saeedi, M. & Markov, I. L. Synthesis and optimization of reversible circuits — a survey. ACM Comput. Surv. 45 (2). 21 (2013)
Borkar, S. Thousand-core chips: a technology perspective. In Proc. Design Automation Conf. 746–749 (ACM, 2007)This paper describes Intel’s thousand-core CPU architecture with an emphasis on fine-grain power management, memory bandwidth, on-die networks, and system resiliency.
Rabaey, J. M., Chandrakasan, A. & Nikolic, B. Digital Integrated Circuits A Design Perspective (Pearson Education, 2003)
Bohr, M. A 30 year retrospective on Dennard’s MOSFET scaling paper. IEEE Solid-State Circ. Soc. Newsl. 12, 11–13 (2007)This paper reviews power scaling of integrated circuits, which held for 30 years, but has now broken down.
Taylor, M. B. Is dark silicon useful? harnessing the four horsemen of the coming dark silicon apocalypse. In Proc. Design Automation Conf. 1131–1136 (ACM, 2012)
Esmaeilzadeh, H., Blem, E. R., St.-Amant, R., Sankaralingam, K. & Burger, D. Power challenges may end the multicore era. Commun. ACM 56, 93–102 (2013)
Yeraswork, Z. 3D stacks and security key for IBM in server market. EE Times http://www.eetimes.com/document.asp?doc_id=1320403 (17 December 2013)
Caldwell, A. E., Kahng, A. B. & Markov, I. L. Hierarchical whitespace allocation in top-down placement. IEEE Trans. Computer-Aided Design Integrated Circ. 22, 716–724 (2003)
Adya, S. N., Markov, I. L. & Villarrubia, P. G. On whitespace and stability in physical synthesis. Integration VLSI J. 39, 340–362 (2006)
Saxena, P., Menezes, N., Cocchini, P. & Kirkpatrick, D. Repeater scaling and its impact on CAD. IEEE Trans. Computer-Aided Design Integrated Circ. 23, 451–463 (2004)
Oestergaard, J., Okholm, J., Lomholt, K. & Toennesen, G. Energy losses of super-conducting power transmission cables in the grid. IEEE Trans. Appl. Supercond. 11, 2375 (2001)
Pinckney, N. R. et al. Limits of parallelism and boosting in dim silicon. IEEE Micro 33, 30–37 (2013)
Kim, S., Ziesler, C. H. & Papaefthymiou, M. C. Charge-recovery computing on silicon. IEEE Trans. Comput. 54, 651–659 (2005)
Dreslinski, R. G., Wieckowski, M., Blaauw, D., Sylvester, D. & Mudge, T. Near-threshold computing: reclaiming Moore’s law through energy efficient integrated circuits. Proc. IEEE 98, 253–266 (2010)
Pendry, J. B. Quantum limits to the flow of information and entropy. J. Phys. Math. Gen. 16, 2161–2171 (1983)
Blencowe, M. P. & Vitelli, V. Universal quantum limits on single-channel information, entropy, and heat flow. Phys. Rev. A 62, 052104 (2000)
Whitney, R. S. Most efficient quantum thermoelectric at finite power output. Phys. Rev. Lett. 112, 130601 (2014)
Zhirnov, V. V., Cavin, R. K., Hutchby, J. A. & Bourianoff, G. I. Limits to binary logic switch scaling—a Gedanken model. Proc. IEEE 91, 1934–1939 (2003)
Wolf, S. A. et al. Spintronics: a spin-based electronics vision for the future. Science 294, 1488–1495 (2001)
Krauss, L. M. & Starkman, G. D. Universal limits on computation. Preprint at http://arxiv.org/abs/astro-ph/0404510 (2004)
Fisher, D. Your favorite parallel algorithms might not be as fast as you think. IEEE Trans. Comput. 37, 211–213 (1988)
Amdahl, G. M. Computer architecture and Amdahl’s law. IEEE Computer 46, 38–46 (2013)
Mak, W.-K. & Chu, C. Rethinking the wirelength benefit of 3-D integration. IEEE Trans. VLSI Syst. 20, 2346–2351 (2012)
Lee, Y.-J., Morrow, P. & Lim, S. K. Ultra high density logic designs using transistor-level monolithic 3D integration. In Proc. Int. Conf. Computer-Aided Design of Integrated Circuits 539–546 (IEEE, 2012)
Sherwin, M. S., Imamoglu, A. & Montroy Quantum computation with quantum dots and terahertz cavity quantum electrodynamics. Phys. Rev. A 60, 3508 (1999)
Shulaker, M. et al. Carbon nanotube computer. Nature 501, 526–530 (2013)
Simonite, T. Intel’s laser chips could make data centers run better. MIT Technol. Rev. (4 September 2013)
Rønnow, T. F. et al. Defining and detecting quantum speedup. Science 20, 1330–1331 (2014)This paper shows how to define and measure quantum speedup, while avoiding pitfalls and overly optimistic results—an empirical study with a D-Wave 2 chip with up to 503 qubits finds no convincing evidence of speed-up.
Shin, S. W., Smith, G., Smolin, J. A. & Vazirani, U. How ‘quantum’ is the D-Wave machine? Preprint at http://arxiv.org/abs/1401.7087 (2014)
Sipser, M. Introduction to the Theory of Computation 3rd edn (Cengage Learning, 2012)
Fortnow, L. The status of the P versus NP problem. Commun. ACM 52, 78–86 (2009)
Markov, I. L. Know your limits: a review of ‘limits to parallel computation: P-completeness theory’. IEEE Design Test 30, 78–83 (2013)
Aaronson, S. Guest column: NP-complete problems and physical reality. SIGACT (ACM Special Interest Group on Algorithms and Computation Theory) News 36, 30–52 (2005)This paper explores the possibility of efficiently solving NP-complete problems using analog, adiabatic and quantum computing, protein folding and soap bubbles, as well as other proposals for physics-based computing— it concludes that this is unlikely, but suggests other benefits of studying such proposals.
Vazirani, V. Approximation Algorithms (Springer, 2002)
Spielman, D. & Teng, S.-H. Smoothed analysis of algorithms: why the simplex algorithm usually takes polynomial time. In Proc. Symp. Theory of Computing 296305 (ACM, 2001)
Getov, V. Computing laws: origins, standing, and impact. IEEE Computer 46, 24–25 (2013)
Metcalfe, B. Metcalfe’s law after 40 years of ethernet. IEEE Computer 46, 26–31 (2013)
Ryan, P. S., Falvey, S. & Merchant, R. When the cloud goes local: the global problem with data localization. IEEE Computer 46, 54–59 (2013)
Wenisch, T. F. & Buyuktosunoglu, A. Energy-aware computing. IEEE Micro 32, 6–8 (2012)
Bachrach, J. & Beal, J. Developing spatial computers. Technical Report MITCSAIL-TR-2007–017 (MIT, 2007)
Rosenbaum, D. Optimal quantum circuits for nearest-neighbor architectures. Preprint at http://arxiv.org/abs/1205.0036; in 8th Conf. on the Theory of Quantum Computation, Communication and Cryptography 294–307 (Schloss Dagstuhl—Leibniz-Zentrum fuer Informatik, 2012)
Patil, D., Azizi, O., Horowitz, M., Ho, R. & Ananthraman, R. Robust energy-efficient adder topologies. In Proc. IEEE Symp. on Computer Arithmetic 16–28 (IEEE, 2007)
Brewer, E. CAP twelve years later: how the ‘rules’ have changed. IEEE Computer 45, 23–29 (2012)
Demmel, J. Communication-avoiding algorithms for linear algebra and beyond. In Proc. Int. Parallel and Distributed Processing Symp. 585 (IEEE, 2013)
Halfill, T. R. Tabula’s time machine. Microprocessor Report (29 March 2010)
Dror, R. O. et al. Overcoming communication latency barriers in massively parallel scientific computation. IEEE Micro 31, 8–19 (2011)
Dean, J. & Barroso, L. A. The tail at scale. Commun. ACM 56, 74–80 (2013)
Barroso, L. A., Clidaras, J. & Hölzle, U. The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines 2nd edn (Synthesis Lectures on Computer Architecture, Morgan & Claypool, 2013)
Balasubramonian, R., Jouppi, N. P. & Muralimanohar, N. Multi-Core Cache Hierarchies (Synthesis Lectures on Computer Architecture, Morgan & Claypool, 2011)
Aaronson, S. & Wigderson, A. Algebrization: a new barrier in complexity theory. ACM Trans. Complexity Theory 1 (1), http://www.scottaaronson.com/papers/alg.pdf (2009)
Avigad, J. & Harrison, J. Formally verified mathematics. Commun. ACM 57, 66–75 (2014)
Asenov, A. Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 m MOSFETs: a 3-D “atomistic” simulation study. IEEE Trans. Electron. Dev. 45, 2505–2513 (1998)
Miranda, M. The threat of semiconductor variability. IEEE Spectrum http://spectrum.ieee.org/semiconductors/design/the-threat-of-semiconductor-variability (2012)
Naeemi, A. et al. BEOL scaling limits and next generation technology prospects. Proc. Design Automation Conf. 1–6. (ACM, 2014)
Devoret, M. H. & Schoelkopf, R. J. Superconducting circuits for quantum information: an outlook. Science 339, 1169–1173 (2013)
This work was supported in part by the Semiconductor Research Corporation (SRC) Task 2264.001 (funded by Intel and IBM), a US Airforce Research Laboratory award (FA8750-11-2-0043), and a US National Science Foundation (NSF) award (1162087).
The author declares no competing financial interests.
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Markov, I. Limits on fundamental limits to computation. Nature 512, 147–154 (2014). https://doi.org/10.1038/nature13570
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