A III–V nanowire channel on silicon for high-performance vertical transistors

Abstract

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time1,2,3,4. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon5,6,7,8,9 because of their high electron mobility and high-quality interface with gate dielectrics10. The idea of surrounding-gate transistors11, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated12,13 because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

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Figure 1: Selective-area growth of InGaAs nanowires on Si(111).
Figure 2: Vertical InGaAs nanowire channel SGT on Si.
Figure 3: Formation and characterization of InGaAs/InP/InAlAs/InGaAs CMS nanowires on Si.
Figure 4: Performance of an SGT using InGaAs/InP/InAlAs/InGaAs CMS nanowire channels on Si.

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Acknowledgements

We thank J. Motohisa, S. Hara, K. Hiruma, T. Hashizume and T. Waho for discussions. We especially thank Y. Hori for instructing us on the current–voltage measurement. This work was financially supported by a Grant-in-Aid for Scientific Research from MEXT and the Japan Science and Technology Agency – PRESTO programme.

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K.T. designed the experiments, made the nanowires by metal–organic vapour phase epitaxy, fabricated the device and analysed all of the data. T.F. planned and supervised the study. M.Y. helped in the epitaxy experiments. All authors discussed the results and commented on the manuscript.

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Correspondence to Katsuhiro Tomioka.

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The authors declare no competing financial interests.

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Tomioka, K., Yoshimura, M. & Fukui, T. A III–V nanowire channel on silicon for high-performance vertical transistors. Nature 488, 189–192 (2012). https://doi.org/10.1038/nature11293

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