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Tunnel field-effect transistors as energy-efficient electronic switches

Abstract

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

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Figure 1: Power challenge and main characteristics of an energy-efficient tunnel FET.
Figure 2: Principle of operation of a TFET.
Figure 3: Band diagrams of heterostructure C-TFETs.
Figure 4: Importance of the material system on TFET performance.
Figure 5: Implementation of all-Si technology boosters.
Figure 6: InAs–Si heterojunction diodes and TFETs for improved performance.
Figure 7: Circuit-level characteristics of low-power TFETs.

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Acknowledgements

Some of this work was supported by the European Commission under the FP7 projects Guardian Angels for a Smarter Life and STEEPER. K. Boucart, L. De Michielis, C. Le Royer, K. Moselund, M. Björk, H. Schmid, W. Riess and P. Solomon are particularly acknowledged for useful discussions and supporting materials.

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Ionescu, A., Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011). https://doi.org/10.1038/nature10679

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