Abstract
A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up1,2,3. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes1,4,5,6,7,8, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array9, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor10,11 owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires12 coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm2. The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input–output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.
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Change history
11 February 2011
Figure 3d in the PDF was corrected on 11 February 2011
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Acknowledgements
We thank D. Bell and N. Antoniou for transmission electron microscopy sample preparation and imaging, Q. Qing for assistance with electrical measurements and J. L. Huang, X. Duan and X. Jiang for helpful discussions. C.M.L. acknowledges support from a National Security Science and Engineering Faculty Fellow award and a contract from the MITRE Corporation. S.D., J.F.K. and J.C.E. acknowledge support by the US government’s Nano-Enabled Technology Initiative and the MITRE Innovation Program.
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C.M.L., J.C.E., S.D., H.Y., H.S.C. and S.N. designed the experiments. H.Y., H.S.C., S.N., Y.H. and J.F.K. performed the experiments. S.D. performed simulations. H.Y., H.S.C., S.N., S.D., J.F.K., J.C.E. and C.M.L. analysed the data and wrote the paper. All authors discussed the results and commented on the manuscript.
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Yan, H., Choe, H., Nam, S. et al. Programmable nanowire circuits for nanoprocessors. Nature 470, 240–244 (2011). https://doi.org/10.1038/nature09749
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DOI: https://doi.org/10.1038/nature09749
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