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High-speed graphene transistors with a self-aligned nanowire gate


Graphene has attracted considerable interest as a potential new electronic material1,2,3,4,5,6,7,8,9,10,11. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics12,13,14,15,16,17,18. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance19,20,21. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co2Si–Al2O3 core–shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm−1) and transconductance (1.27 mS μm−1) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of fT = 100–300 GHz, with the extrinsic fT (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic fT of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths10.

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Figure 1: Schematic illustration of a high-speed graphene transistor with a Co 2 Si–Al 2 O 3 core–shell nanowire as the self-aligned top-gate.
Figure 2: Characterization of Co 2 Si and Co 2 Si–Al 2 O 3 core–shell nanowires.
Figure 3: Room-temperature electrical characteristics of the graphene transistors with a self-aligned nanowire gate.
Figure 4: Measured small-signal current gain | h 21 | as a function of frequency f at V ds = −1 V.


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We thank A. Jooyaie and S. Martin for discussions. We also acknowledge the Electron Imaging Center for Nanomachines at UCLA for TEM technical support and the Nanoelectronics Research Facility at UCLA for device fabrication technical support. X.D. acknowledges financial support by the NSF CAREER award 0956171 and the NIH Director’s New Innovator Award Program, part of the NIH Roadmap for Medical Research, through grant number 1DP2OD004342-01.

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Authors and Affiliations



X.D conceived the research. X.D. and L.L. designed the experiments. L.L. performed all the experiments (including material synthesis, device fabrication, and d.c. and radio-frequency characterization) and data analysis. Y.-C.L. contributed to material synthesis, material and device structure characterization, and radio-frequency analysis. M.B. contributed to radio-frequency characterization and analysis. R.C. and Y.L. contributed to d.c. and radio-frequency analysis. J.B. contributed to device fabrication. Y.Q. contributed to material synthesis. X.D. and L.L. co-wrote the paper. All authors discussed the results and commented on the manuscript.

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Correspondence to Xiangfeng Duan.

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The authors declare no competing financial interests.

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This file contains Supplementary Methods, Supplementary Figures 1-8 with legends, Supplementary Tables 1-2 and additional references. (PDF 609 kb)

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Liao, L., Lin, YC., Bao, M. et al. High-speed graphene transistors with a self-aligned nanowire gate. Nature 467, 305–308 (2010).

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