The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates1. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry2. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm2 V-1 s-1, subthreshold slopes as low as 140 m V dec-1, operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 105, switching speeds in the kilohertz range even for coarse (∼100-μm) device geometries, and good mechanical flexibility—all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.
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We thank T. Banks, K. Colravy and D. Sievers for help with the processing. This material is based upon work supported by the US National Science Foundation (NIRT-0403489), the US Department of Energy (DE-FG02-07ER46471), Motorola, Inc., the Frederick-Seitz Materials Research Laboratory and the Center for Microanalysis of Materials (DE-FG02-07ER46453 and DE-FG02-07ER46471) at the University of Illinois. Q.C. acknowledges fellowship support from the Department of Chemistry at the University of Illinois. N.P., J.P.K., M.A. and K.R. acknowledge support from the Network for Computational Nanotechnology, which is supported by the National Science Foundation under cooperative agreement EEC-0634750. J.P.K. acknowledges fellowship support from the Intel Foundation.
Author Contributions Q.C., H.K. and J.A.R. designed the experiments. Q.C., H.K. and C.W. performed the experiments. Q.C., N.P., J.P.K., M.S., K.R., M.A.A. and J.A.R. analysed the data. Q.C. and J.A.R. wrote the paper.
The file contains Supplementary Discussion, which presents results on channel length scaling, gate capacitance measurements, distribution of device on/off ratios, the dependence of off-state current on drain-source voltage, distribution of effective device mobility and subthreshold swing, switching speed characteristics of the four-bit decoder circuit, operational stability test of SWNT TFTs, and some estimations on device properties, Supplementary Table 1, which gives fitting parameters used in HSPICE device simulations, Supplementary Figures and Legends 1-9, and additional references, which accompany the Supplementary Discussion. (PDF 2517 kb)
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Cao, Q., Kim, Hs., Pimparkar, N. et al. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature 454, 495–500 (2008). https://doi.org/10.1038/nature07110
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