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Spin-based logic in semiconductors for reconfigurable large-scale circuits


Research in semiconductor spintronics aims to extend the scope of conventional electronics by using the spin degree of freedom of an electron in addition to its charge1. Significant scientific advances in this area have been reported, such as the development of diluted ferromagnetic semiconductors2,3, spin injection into semiconductors from ferromagnetic metals4,5,6,7,8 and discoveries of new physical phenomena involving electron spin9,10. Yet no viable means of developing spintronics in semiconductors has been presented. Here we report a theoretical design that is a conceptual step forward—spin accumulation is used as the basis of a semiconductor computer circuit. Although the giant magnetoresistance effect in metals11,12 has already been commercially exploited, it does not extend to semiconductor/ferromagnet systems, because the effect is too weak for logic operations. We overcome this obstacle by using spin accumulation rather than spin flow13,14,15. The basic element in our design is a logic gate that consists of a semiconductor structure with multiple magnetic contacts; this serves to perform fast and reprogrammable logic operations in a noisy, room-temperature environment. We then introduce a method to interconnect a large number of these gates to form a ‘spin computer’. As the shrinking of conventional complementary metal-oxide–semiconductor (CMOS) transistors reaches its intrinsic limit, greater computational capability will mean an increase in both circuit area and power dissipation. Our spin-based approach may provide wide margins for further scaling and also greater computational capability per gate.

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Figure 1: Design of the reprogrammable magnetologic gate.
Figure 2: Modelled electrical behaviour of a magnetologic gate set for NAND(X,Y).
Figure 3: Proposed logic cascading scheme.


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We thank B. Dalal for suggestions regarding the logic cascading scheme. This work was supported by the National Science Foundation.

Author Contributions H.D. and L.J.S. developed the proposed idea of spin computation. P.D. designed the cascading scheme. Ł.C. formulated the time-dependent spin-diffusion transport.

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Correspondence to H. Dery.

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Supplementary information

Supplementary Information

The first section ‘Magnetologic gates for high speed electronics’ contains the discussion of the ways in which the signal-to-noise can be improved, and it discusses the different capacitive parasitic effects present in the system. The second section ‘Thyristor latch’ contains a description of the thyristor latch which we use to convert the transient current into a voltage. The third section ‘Power budgeting’ contains the calculation of the power dissipated by a system of ~106 magnetologic gates. The fourth section ‘Magnetization errant dynamics: data retention, write fault and half selection’ qualitatively explains how the possible sources of errors in magnetic random access memories (due to magnetization switching) are eliminated in our spin-logic design. The fifth section contains Supplementary Methods with a detailed account of the time-dependent lateral diffusion equations which we have used in our calculations (figure 2 of the main text). (PDF 560 kb)

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Dery, H., Dalal, P., Cywiński, Ł. et al. Spin-based logic in semiconductors for reconfigurable large-scale circuits. Nature 447, 573–576 (2007).

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