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Ge/Si nanowire heterostructures as high-performance field-effect transistors


Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

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Figure 1: Ge/Si core/shell NWFET.
Figure 2: Characteristics of high-performance Ge/Si NWFET.
Figure 3: Benchmark and comparison of Ge/Si FETs.
Figure 4: Control of threshold voltage and ambipolar conduction through device design.


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We thank C. Y. Wen for help with cross-sectional TEM study and M. Radosavljevic for discussions. C.M.L. acknowledges support of this work by the Defense Advanced Projects Research Agency and Intel. Author Contributions J.X., W.L., Y.H., Y.W. and H.Y. performed the experiments. J.X. and W.L. performed data analyses. J.X., W.L. and C.M.L. designed the experiments, discussed the interpretation of results and co-wrote the paper.

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Correspondence to Charles M. Lieber.

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Supplementary information

Supplementary Figure 1

This figure shows the dependence of the device inverses-transconductance (Rm = 1/gm) as a function of channel length up to 1000 nm. The linear increase is consistent with the charge control model, and yields an average mobility of 640 cm2/V-s. (PDF 24 kb)

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Xiang, J., Lu, W., Hu, Y. et al. Ge/Si nanowire heterostructures as high-performance field-effect transistors. Nature 441, 489–493 (2006).

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