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Two-dimensional semiconductors for transistors

Nature Reviews Materials volume 1, Article number: 16052 (2016) | Download Citation

Abstract

In the quest for higher performance, the dimensions of field-effect transistors (FETs) continue to decrease. However, the reduction in size of FETs comprising 3D semiconductors is limited by the rate at which heat, generated from static power, is dissipated. The increase in static power and the leakage of current between the source and drain electrodes that causes this increase, are referred to as short-channel effects. In FETs with channels made from 2D semiconductors, leakage current is almost eliminated because all electrons are confined in atomically thin channels and, hence, are uniformly influenced by the gate voltage. In this Review, we provide a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FETs in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene. We also describe tunnelling FETs that possess extremely low-power switching behaviour and explain how they can be realized using heterostructures of 2D semiconductors.

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Acknowledgements

M.C. acknowledges financial support from US National Science Foundation ECCS 1128335. D.J. would like to acknowledge financial support from the STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA, and by the Office of Naval Research (ONR), the Air Force Office of Scientific Research (AFOSR), and the National Science Foundation (NSF).

Author information

Affiliations

  1. Materials Science & Engineering, Rutgers University, Piscataway, New Jersey 08854, USA.

    • Manish Chhowalla
  2. Electrical and Computer Engineering, Rutgers University, Piscataway, New Jersey 08854, USA.

    • Manish Chhowalla
  3. Electrical and Computer Engineering, Cornell University, Ithaca, New York 14853, USA.

    • Debdeep Jena
  4. Materials Science and Engineering, Cornell University, Ithaca, New York 14853, USA.

    • Debdeep Jena
  5. School of Materials Science and Engineering, Nanyang Technological University, Nanyang Avenue 639798, Singapore.

    • Hua Zhang

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Competing interests

The authors declare no competing interests.

Corresponding authors

Correspondence to Manish Chhowalla or Debdeep Jena.

Supplementary information

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  1. 1.

    Supplementary information S1 (box)

    Quantitative description of FET

  2. 2.

    Supplementary information S2 (figure)

    Flowchart for assessing performance of FETs

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https://doi.org/10.1038/natrevmats.2016.52

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