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Carbon-nanotube computer scaled up

Electronic devices that are based on carbon nanotubes have the potential to be more energy efficient than their silicon counterparts, but have been restricted in functionality. This limitation has now been overcome.
Franz Kreupl is in the Department of Hybrid Electronic Systems, Technical University of Munich, 80333 Munich, Germany.
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For many decades, progress in electronics has been driven by a gradual reduction in the size of silicon transistors (electronic switches). However, this scaling is becoming increasingly difficult and is now yielding diminishing returns. Transistors based on semiconducting carbon nanotubes are clear front runners as replacements for silicon transistors in advanced microelectronic devices. But imperfections inherent in carbon nanotubes, and challenges in handling these tiny objects, have prevented their use in real-world microelectronic applications. Writing in Nature, Hills et al.1 report a major advance in this field: a 16-bit computer that is built entirely from carbon-nanotube transistors.

To achieve this milestone, the authors needed to develop a viable nanotube-transistor technology that provides two kinds of transistor: p-type metal–oxide–semiconductor (PMOS) and n-type metal–oxide–semiconductor (NMOS). In digital electronics, a computation is divided into a sequence of elementary (logic) operations that are carried out by components called logic circuits. The present design of these circuits in the electronics industry is based on complementary metal–oxide–semiconductor (CMOS) technology, which requires both PMOS and NMOS transistors.

A PMOS (or NMOS) transistor is switched on when a negative (or positive) voltage is applied to an electrode known as the gate. This electrode controls the conductivity of the channel (in this case, formed by carbon nanotubes) between two other electrodes (the source and the drain). When a PMOS transistor and an NMOS transistor are interconnected in series, the result is an element called an inverter (Fig. 1). If a low voltage is applied to such an inverter, the output voltage will be high, and vice versa. This element is the basic ingredient of all the logic circuits used in Hills and colleagues’ computer.

Figure 1 | A carbon-nanotube inverter. a, Hills et al.1 demonstrate a computer that uses basic elements called inverters. Each of these inverters contains two kinds of transistor (electronic switch): a p-type metal–oxide–semiconductor (PMOS) transistor and an n-type metal–oxide–semiconductor (NMOS) transistor. These transistors are interconnected in series and are formed on a silicon oxide substrate. Each transistor consists of three electrodes known as the source, the gate and the drain; the source and the drain are separated by a channel that is formed of semiconducting carbon nanotubes. The micrometre-scale width and length of a channel are indicated. b, If a low voltage is applied to the inverter, the output voltage will be high, and vice versa.

The authors made their transistors by forming a network of randomly distributed, high-purity (99.99%) semiconducting nanotubes on a substrate. The formation process resembles pouring a bowl of cooked spaghetti onto a surface and then removing all the strands that are not in direct contact with the surface. The result is a substrate covered with roughly a single-layer of randomly oriented nanotubes.

Hills et al. then deposited metal on the nanotubes to connect them to the source and the drain. The work function of this metal (the energy needed to remove an electron from its surface) depended on whether the device was a PMOS or an NMOS transistor. The authors covered the rest of each nanotube with carefully selected and trimmed oxide materials, to isolate the nanotubes from their surroundings and to adjust their properties. In principle, the substrate does not need to be made of silicon; it simply needs to be flat. Moreover, the processing happens at relatively low temperatures (about 200–325 °C), so that stacking of further functional layers would easily be possible.

Contemporary computer design is based on libraries of standard cells — sets of logic operations that can be interconnected for greater functionality. Hills and colleagues devised all the standard cells required to make their computer’s architecture using commercially available, conventional design tools. Because the semiconducting nanotubes had a purity of 99.99%, about 0.01% of them were metallic (non-semiconducting) and could have jeopardized the circuits. However, certain combinations of standard cells are more vulnerable to the presence of metallic nanotubes than are others. The authors therefore enforced modified design rules that excluded such vulnerable combinations. Equipped with these tools, they were able to design, fabricate and test their computer by letting it execute ‘Hello, World’ — a simple program that outputs the message “Hello, World” when run.

Hills and colleagues’ nanotube computer is based on CMOS technology, runs 32-bit instructions on 16-bit data and has a transistor-channel length of roughly 1.5 micrometres. It can therefore be compared to the silicon-based Intel 80386 processor, which was introduced in 1985 and had similar specifications. The early 80386 could process its instructions at a frequency of 16 megahertz (see go.nature.com/33clr1a), whereas the nanotube computer has a maximum processing frequency of about 1 MHz. The reason for this difference lies in the capacitances (charge-storage abilities) of the electronic components, and in the amount of current that the smallest transistor can deliver.

Digital logic simply involves charging and discharging the transistor gates and the interconnects. The speed of charging and discharging depends on the amount of current that a transistor can provide, which is related to the width and length of the transistor. A well-designed silicon transistor can deliver roughly one milliampere of current per micrometre of width (1 mA µm−1) (see go.nature.com/2z4wjda). By contrast, the typical nanotube transistors used by Hills et al. can provide only about 6 µA µm−1. This is the main feature that will need improvement in future versions of the computer.

The first step for increasing the electric current is to reduce the transistor-channel length. It has already been demonstrated2 that the channel lengths of nanotube transistors can be scaled down to 5 nm. The second step is to increase the density of nanotubes in each channel from as little as 10 nanotubes per micrometre to 500 nanotubes per micrometre. For these networks of randomly distributed nanotubes, there might be an upper limit on the achievable density, but a deposition technique has been shown3 to boost the current in such networks to 1.7 mA µm−1. The third step is to decrease the width of the transistors, and thereby the widths of the source and the drain, which would allow these electrodes to be charged and discharged more quickly4. These scaled-down transistors are essential for nanotube-based CMOS technology that operates at gigahertz frequencies5.

Hills and colleagues’ achievement is based on averaging the performances of several nanotubes in each transistor channel. In the large-scale nanotube computer of the distant future, the PMOS and NMOS transistors will contain only one nanotube. These nanotubes will need to be semiconducting: no design trick will provide a workaround if one of the two nanotubes in an inverter is metallic.

The authors’ work is a great accomplishment that touches on many research topics — from materials science to processing technology, and from circuit design to electrical testing. However, more effort is required before the team will need a sales department.

Nature 572, 588-589 (2019)

doi: 10.1038/d41586-019-02519-2

References

  1. 1.

    Hills, G. et al. Nature 572, 595–602 (2019).

  2. 2.

    Qiu, C. et al. Science 355, 271–276 (2017).

  3. 3.

    Zhong, D., Xiao, M., Zhang, Z. & Peng, L.-M. 2017 IEEE Int. Electron Devices Meet. 5.6.1–5.6.4 (2017).

  4. 4.

    Cao, Q., Tersoff, J., Farmer, D. B., Zhu, Y. & Han, S.-J. Science 356, 1369–1372 (2017).

  5. 5.

    Han, S.-J. et al. Nature Nanotechnol. 12, 861–865 (2017).

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