Over the past three decades, as the components that make up integrated circuits have been made smaller and smaller, the power of computer chips has grown exponentially, even as their cost has fallen drastically. But sooner rather than later — by around 2020, according to one estimate1 — the scaling-down process will become difficult to maintain2,3. The energy required to represent a bit of information will become larger than the heat that can be carried away from a tiny circuit element; what's more, as devices approach the size of atoms, quantum-physical phenomena will become important, changing even the ground rules of how bits are processed. Writing in Applied Physics Letters4, Nishiguchi et al. detail what might be one way to circumvent, and even exploit, these issues. They describe a circuit that allows them to perform the computing operation of pattern matching by harnessing the stochastic, quantum-mechanical tunnelling of single electrons into a transistor5.

Pattern recognition is a natural enough task for people, but is often difficult for computers. We would like our computer processors to be like us and recognize an object (a cat or a dog, say) in a photographic image, understand the meaning of spoken words, or translate efficiently from one language to another. But pattern recognition also has more abstract, fundamental uses: extracting a simple conclusion from a great body of input data, for instance.

Nishiguchi et al.4 build on previous work6,7,8 to construct a simple pattern-matching circuit using a basic building-block of two transistors (more precisely, metal–oxide–semiconductor field-effect transistors, or MOSFETs) patterned on a silicon-on-insulator wafer. They trap and store single electrons on the first of these nanoscale transistors, the 'T-FET'. They are able to reduce the rate at which electrons tunnel quantum-mechanically into a storage node on the T-FET to very low levels of around one per second. The authors show that the trapped electrons obey Poisson statistics, and represent a statistically random source of events that can be used for stochastic signal processing9.

The job of the second transistor that makes up the authors' processor, the 'D-FET', is to detect the number of electrons stored in the T-FET. It does this through a capacitative coupling: as the number of electrons stored in the T-FET increases, the current passing through the D-FET is progressively reduced. The coupling is sensitive enough that the tunnelling of a single electron into the T-FET is registered as a discrete drop in current in the D-FET.

To perform pattern matching, the individual bits of an input image must be compared with those of a reference image. Nishiguchi and colleagues set an input bit, i, to 0 or 1 by stepping the input 'source' voltage of the T-FET. Similarly, they set a reference bit, r, by changing the T-FET's 'gate' voltage, which controls the passage of current from the source into the storage node (Fig. 1). When i = 0, the tunnelling rate into the T-FET is negligible. When i = 1, tunnelling occurs, and the number of electrons stored in the T-FET slowly builds up. The precise rate of this tunnelling is controlled by the gate voltage, and thus the reference bit: it is large when r = 1, and small when r = 0.

Figure 1: Dual processor.
figure 1

Nishiguchi and colleagues' pattern-recognition processor4 uses two basic components that each consist of two capacitatively coupled transistors: a transfer transistor (T-FET) and a detector transistor (D-FET). The probability that an electron will tunnel from the source of the T-FET, under the gate and into the storage node is determined by the source voltage, which is set by the value of a bit i in the input image, and by the gate voltage, which is set by a bit r in the reference image. The more electrons accumulate in the T-FET storage node, the lower the current that flows through the capacitatively coupled D-FET. In the instance depicted, both the input and reference bits are turned on, i = r = 1, and electrons accumulate in the storage node, reducing the detector current. The second unit (right) is fed with the inverse inputs of the first, ī and r̄. If the original inputs were matched at 0, the inputs here would be 1, and this half of the processor would record the depleted current characteristic of matched bits. (Figure adapted from ref. 1.)

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Essentially, this set-up creates a detector that flags up when the input and reference bits are both on, i = r = 1: in this case, electrons build up in the T-FET particularly fast, and the current passing through the D-FET decreases rapidly. To recognize a pattern of bits such as that in an image — a series of 0s and 1s — a second unit is required that responds similarly when i = r = 0. This can be done simply by setting the T-FET source and gate voltages on the second unit to represent the logical inverses of whatever the input and reference bits are on the first unit. The output currents from both D-FETs are then added together. The result is the equivalent of an exclusive NOR logic gate: it flags up through a sharp drop in current whenever the input and reference bits match up (whatever the values of those bits are), but does not respond when they differ.

The authors demonstrate the principle of pattern matching using the circuit by feeding it sequentially with four bits representing an image of the letter n, and comparing it with four four-bit reference sequences encoding the letters n, c, o and u (Fig. 2a). The total error was found in each case by summing the number of electrons collected in the two T-FETs, as deduced from the drop in summed D-FET current. When the reference coding for n was used, the current drop was by far the greatest (Fig. 2b).

Figure 2: Comparing letters.
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a, Images of the letters n, c, o and u can be translated into sequences of four bits (working clockwise from the left of each letter). b, Nishiguchi et al.4 test their pattern-matching processor by sequentially feeding in the source image bits encoding n, and comparing them in turn with reference bit strings for n, c, o and u. The first bit in each reference sequence is 1, so the technique cannot distinguish between them — the detected current falls similarly for each. But as subsequent image and reference bits differ, the currents registered for those reference images increase — until after all four bits, the 'winning' reference image, n, is clearly marked by its low detector-current signal. The individual steps in the current record correspond to the tunnelling of individual electrons into the processor; the sharp steps in output current at the transitions between bits occur because the D-FET picks up changes in T-FET source and gate voltage. (Figure adapted from ref. 1.)

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Nishiguchi and colleagues' advance is opportune for two reasons. First, it comes at a time when computing is moving away from single processors towards many processors operating in parallel. 'Cloud' computing, which uses very many parallel processors, is what allows search engines such as Google to provide rapid answers to our web enquiries, and now even many laptop computers contain chips that have two or more processors, or 'cores'. In this multi-processor environment, it is increasingly likely that we would wish to add special circuits dedicated to a single purpose, such as the fundamental task of pattern recognition.

Second, we are now recognizing that entirely new chip architectures and new approaches to computation are needed to continue the rapid growth in computing power to which we have become accustomed1,2,3. To that end, the semiconductor industry has developed a set of goals3 for research aimed at producing truly nanoscale switches with low power requirements that work at room temperature. Nishiguchi and colleagues' circuit is a meaningful step in this direction: it uses silicon-on-insulator circuits that are compatible with conventional silicon technology, it works at room temperature, and it can respond to the stimulus of just a single electron.

In its present form, this work4 represents just a proof of principle. But extended to a system that can handle many bits, such single-electron circuits that exploit stochastic quantum-mechanical effects to produce low-power devices could be an important part of a brave new electronic future.