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Imprints offer Moore

Naturevolume 417pages802803 (2002) | Download Citation


The cost of making chip components smaller using photolithographic printing might soon invalidate Moore's law. A new imprinting technique that can reproduce features as small as 10 nm could save it.

Progress in microelectronics is celebrated in Moore's law, which states that the number of transistors that can be integrated on a single silicon chip doubles every 18 months1. Moore has also put forward two corollaries to the basic law: that everything gets better as it gets smaller, and that the cost of the manufacturing technology increases geometrically with time2.

The semiconductor industry has maintained the validity of Moore's law and of the first corollary by keeping the total chip size about constant and cramming in more, smaller components (transistors and the wires connecting them). The implication of the second corollary is that the increased cost of the manufacturing technology is a threat to the law's continued validity; indeed, if the cost per transistor starts to increase, it could well be the end of the law. But a new imprinting technology for the production of silicon chips, introduced by Chou et al.3 on page 835 of this issue, could keep us on track.

The dominant contributor to the cost of manufacturing chips is the patterning technology, often known as photolithography, in which the image of a chip pattern is optically focused onto a thin film of light-sensitive polymer, or 'resist', on a silicon wafer (Fig. 1a). Selectively dissolving away either the exposed or the unexposed regions of the resist leaves a relief image on the silicon, which can then be transferred, by etching, to the underlying material to make the components that comprise the chip. A sequence of between 4 and 30 overlaid photolithographic levels is needed to make a complete chip.

Figure 1: A new recipe for silicon chips?
Figure 1

a, Currently, electronic components are integrated on a silicon chip using photolithography. The chip pattern is captured on a 'resist' (similar to photographic film) as ultraviolet light is shone through a mask bearing the pattern. After the resist is developed, the silicon layer beneath is etched using the resist pattern as a guide. The resist is removed and the chip pattern in the silicon remains. The future of photolithography, however, may be limited. The projection optics that focus the light onto the resist are costly, and the demand for ever smaller components is unlikely to be met — the smallest features possible at the moment are around 100 nm in size. b, Chou et al.3 have developed an imprinting technique that they call 'LADI' (laser-assisted direct imprint). Laser light shone through a quartz mask above the silicon surface melts the top layer of silicon. The mask is pressed into the molten layer. When the mask is removed, an accurate imprint of the component design remains in the silicon, with detail rendered at the 10-nm level.

The key piece of equipment is the optical system, similar in principle to that of a microscope, by which the image is focused onto the resist. Known as a 'stepper', it is complicated and expensive, currently costing more than US$10 million. In one minute, a stepper may be required to expose 60 images, each 2 × 2 cm and containing more than 10 billion features. The smallest possible feature is a square with sides 130 nm long, and the accuracies (or tolerances) of the size and position of features are around 25 nm and 65 nm, respectively; moreover, there must be no detectable defects within the image. To follow Moore's law, the minimum feature size and the respective tolerances will need to be halved over the next three years, while still maintaining the same image size and speed of the process. Over the same period, the stepper cost is projected to rise to more than $20 million. But with four times as many features created in a single image, the required reduction in cost per exposed feature could still be met.

Physicists will notice that a projected feature size of 65 nm is beyond Rayleigh's resolution limit for a microscope — the minimum distance that can be resolved owing to the effects of diffraction. (This limit is about 110 nm for ultraviolet light with a wavelength of 193 nm.) To achieve this resolution is difficult and expensive, though not impossible, and it is not clear that we can keep reducing feature size and the cost per exposed feature by continuing to push the technique of optical projection. If progress falters, Moore's law will fail and this could be disastrous for the semiconductor industry.

Thus industry is investing in 'next generation lithography', in particular in two favoured technologies, electron-projection and extreme-ultraviolet lithography. Both rely on high-resolution focusing of a projected image. However, progress has been slow and expensive, and there are doubts that either technique can maintain Moore's law.

But a new technology based on conventional, mechanical printing could eliminate the focusing problem altogether. Derived from the imprinting process used to manufacture compact disks, this process can generate sub-micrometre features over an area of 100 cm2 in less than a second at a cost of about 50 cents — that's between two and three orders of magnitude less than the cost of optical projection. In 1996, Chou and colleagues demonstrated4 that a modification of this technique could generate 10-nm features over an image field of about 3 cm2, an extraordinary combination of minimum feature size and image size.

There have been other significant advances, such as the development by Whitesides and colleagues5 of another mechanical printing process, 'soft lithography', with which features smaller than 100 nm can be printed on non-flat surfaces. In 1998, the US Defense Advanced Research Projects Agency launched a research programme on 'molecular-level, large-area printing' (MLP). And the semiconductor industry is beginning to take notice; results are emerging from a joint development programme in this area launched by Motorola and the University of Texas6.

The latest development reported here by Chou et al.3 is one of the most exciting. They have demonstrated that, instead of imprinting in a thin plastic resist film, they can pattern silicon directly by a combination of imprinting and flood illumination (Fig. 1b). They call the process 'LADI', for laser-assisted direct imprint. The printing mask is made of quartz, with a relief image on the surface that presses against the silicon. Flashing laser light through the mask causes the top, sub-micrometre layer of silicon to melt momentarily and take on the shape of the relief image of the mask. The mask is then separated from the silicon, apparently without any unwanted adhesion between the silicon and the quartz.

Chou et al. created features of 140-nm dimension (the limit of their mask). But detail at the level of 10 nm on these features was also replicated, indicating the extraordinary resolution of the process. This technique can also be used for patterning polycrystalline films of silicon, one of the most critical steps in patterning silicon chips. Because there is no need for expensive focusing optics, the printing equipment is much simpler than a stepper. And the absence of a resist eliminates that cost too.

But there are technical challenges to be met. Defects caused and propagated by contact led to the abandoning of contact photo-printing in the early history (pre-1970) of silicon chips, so we might expect similar problems here. But in the decades since, there have been tremendous advances in managing defects. Making a suitable mask with features as small as those required on the wafer is a challenge, but there is at least one tool, Nippon Telephone and Telegraph's experimental electron-beam system 'EBX-3', that seems to be up to the task.

Thus, on grounds of cost, speed and resolution, LADI, or some other form of mechanical printing, may displace optical projection as the preferred manufacturing technology for fashioning silicon chips. So we might expect Moore's law to hold for, maybe, another two decades.


  1. 1

    Moore, G. E. Electronics 38, 19 April (1965);

  2. 2

    Moore, G. E. Wired 5.05 (1997).

  3. 3

    Chou, S. Y., Keimel, C. & Gu, J. Nature 417, 835–837 (2002).

  4. 4

    Chou, S. Y., Krauss, P. R. & Renstrom, P. S. Science 272, 85–87 (1996).

  5. 5

    Xia, Y. & Whitesides, G. Annu. Rev. Mater. Sci. 28, 153–184 (1998).

  6. 6

    Resnik, D. J. et al. in Emerging Lithographic Technologies VI (ed. Engelstad, R. L.) Proc. SPIE 4688 (in the press).

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  1. Department of Electrical Engineering, Stanford University, Stanford, 94305, California, USA

    • R. Fabian Pease


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