Metal–oxide–semiconductor field-effect transistor with a vacuum channel

Journal name:
Nature Nanotechnology
Year published:
Published online


High-speed electronic devices rely on short carrier transport times, which are usually achieved by decreasing the channel length and/or increasing the carrier velocity. Ideally, the carriers enter into a ballistic transport regime in which they are not scattered1. However, it is difficult to achieve ballistic transport in a solid-state medium because the high electric fields used to increase the carrier velocity also increase scattering2. Vacuum is an ideal medium for ballistic transport, but vacuum electronic devices commonly suffer from low emission currents and high operating voltages. Here, we report the fabrication of a low-voltage field-effect transistor with a vertical vacuum channel (channel length of ~20 nm) etched into a metal–oxide–semiconductor substrate. We measure a transconductance of 20 nS µm–1, an on/off ratio of 500 and a turn-on gate voltage of 0.5 V under ambient conditions. Coulombic repulsion in the two-dimensional electron system3 at the interface between the oxide and the metal or the semiconductor reduces the energy barrier to electron emission, leading to a high emission current density (~1 × 105 A cm–2) under a bias of only 1 V. The emission of two-dimensional electron systems into vacuum channels could enable a new class of low-power, high-speed transistors.

At a glance


  1. Ballistic transport of electrons in nano-void channels in silicon MOS.
    Figure 1: Ballistic transport of electrons in nano-void channels in silicon MOS.

    a, Schematic of a nano-void channel fabricated by FIB etching (left) and SEM image of a square well (1 × 1 µm2) etched to a depth of 1 µm (right). Scale bar, 1 µm. b, Schematics of electron emission and transport in nano-void channels: n-Si (left) and p-Si (right) substrate samples under forward bias. Note the electron emission from the edge of the 2DES formed in the cathode (silicon, left; aluminium, right). ce, Measured IV characteristics of nano-void channels: square wells (c, perimeters of 2, 4 or 8 µm) formed on p-Si; a 2-µm-perimeter well (d) formed on p-Si with different etch depths (1 or 2 µm); square wells (e, perimeters of 2, 4 or 8 µm) formed on n-Si. Dashed lines indicate slopes of 1.5 (forward) or 1.0 (reverse).

  2. Energy band diagrams.
    Figure 2: Energy band diagrams.

    a, Two-dimensional electron or hole systems induced across the oxide layer. b, Schematic illustration of electron potential (red) and energy barrier (blue) profiles on the plane of the 2DES layer at the silicon/SiO2 interface (y-axis direction). c, Schematic energy band diagram of a p-Si sample at 1 V forward bias. Where q is the electron charge, φM and φs are the work function of the metal and the Fermi level of the semiconductor, respectively, and Ev, Ef, Ec, Ei and Evac are the energy of the valence band, Fermi level, conduction band, intrinsic Fermi level and vacuum level, respectively. d, Schematic energy band diagram of n-Si sample at 1 V forward bias. The 2DES induced in the cathode (aluminium for p-Si; silicon for n-Si substrate) serves as a reservoir of electrons that are readily available for emission through the edge under forward bias.

  3. Measurement of electron capture efficiency at anode edges.
    Figure 3: Measurement of electron capture efficiency at anode edges.

    a, Schematic of channel top (aluminium electrode with a square opening) covered with a gallium droplet electrode (left). Optical micrograph of a gallium droplet pressed by a tungsten probe (right). Scale bars, 400 µm (top), 200 µm (bottom). b, Channel current measured with and without a gallium cover for a 0.5 × 0.5 × 1 µm3 well sample formed on the n-Si substrate. The measured channel current was found to be two orders of magnitude greater than that without a cover.

  4. Nano-void channel FET.
    Figure 4: Nano-void channel FET.

    a, Device structure formed on a silicon MOS substrate (inset: plan-view SEM image of a nanochannel fabricated by FIB; scale bar, 30 µm). A thin layer of ITO was introduced into the MOS capacitor structure as a gate electrode, forming a vertically stacked five-layer structure: 20 nm aluminium/30 nm SiO2/20 nm ITO/20 nm SiO2/p-Si substrate. A nano-void channel of square cross-section (0.5 × 0.5 µm2, 1 × 1 µm2 and 2 × 2 µm2) was formed by FIB etching of the stacked layers. b, Operation of a nano-vacuum FET. The ITO gate layer is designed to control electron inversion layer formation in the p-Si substrate. c, Schematic energy band diagram at zero bias. d, IV characteristics of a nanochannel FET (1 × 1 µm2) measured in common source (cathode) mode. For VGS > 0.4 V, the channel current is on. e, IG versus VGS measured at VDS = 1 V or 2 V. f, ID versus VGS measured at VDS = 1 V or 2 V.


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  1. Department of Electrical and Computer Engineering and Petersen Institute of NanoScience and Engineering, 1140 Benedum, University of Pittsburgh, Pittsburgh, Pennsylvania 15261, USA

    • Siwapon Srisonphan,
    • Yun Suk Jung &
    • Hong Koo Kim


S.S. carried out device processing and characterization. Y.S.J. performed FIB etching for nano-void channel fabrication. H.K.K. designed the study, provided theoretical guidance, and supervised the entire project. H.K.K. wrote the manuscript with comments from S.S. and Y.S.J.

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