High-density integration of carbon nanotubes via chemical self-assembly

Journal name:
Nature Nanotechnology
Year published:
Published online


Carbon nanotubes have potential in the development of high-speed and power-efficient logic applications1, 2, 3, 4, 5, 6, 7. However, for such technologies to be viable, a high density of semiconducting nanotubes must be placed at precise locations on a substrate. Here, we show that ion-exchange chemistry can be used to fabricate arrays of individually positioned carbon nanotubes with a density as high as 1 × 109 cm−2—two orders of magnitude higher than previous reports8, 9. With this approach, we assembled a high density of carbon-nanotube transistors in a conventional semiconductor fabrication line and then electrically tested more than 10,000 devices in a single chip. The ability to characterize such large distributions of nanotube devices is crucial for analysing transistor performance, yield and semiconducting nanotube purity.

At a glance


  1. Selective placement of carbon nanotubes by an ion-exchange process.
    Figure 1: Selective placement of carbon nanotubes by an ion-exchange process.

    a, Schematic of nanotube placement on the surface monolayer, which is selectively coated on the HfO2 regions. The iodine ion in the end group of the NMPI monolayer is exchanged by the negatively charged SDS surfactant wrapping the nanotubes; Na+ in SDS and I in NMPI are dissolved into solution as a sodium iodide. The thickness of SiO2 is 10 nm and the width of the HfO2 trenches varies from 70 nm to 200 nm. The P++ Si layer is a highly doped p-type Si substrate. b, SEM image of nanotubes deposited on an open HfO2 area, showing extremely high density and excellent selectivity (scale bar, 2 µm). c,d, SEM image (c) and AFM (phase) image (d) of the nanotubes selectively deposited on an array of 200-nm-wide HfO2 trenches. Good density and selectivity are maintained on these narrower trenches. Scale bars are 500 nm.

  2. High density of individually positioned carbon nanotubes.
    Figure 2: High density of individually positioned carbon nanotubes.

    a, Plots of angular alignment of individual nanotubes versus length of the nanotube for trenches of three different widths (W = 200 nm, 100 nm, 70 nm). Inset: schematic showing how the angular alignment θ is defined (0° is perfect alignment in a trench). By reducing the trench width to 70 nm, the angular variation was reduced from ±75° to less than ±30°. b, SEM image of nanotubes selectively placed and well-aligned in an array of 70-nm-wide HfO2 trenches with a 200 nm pitch (scale bar, 400 nm). c, SEM image of nanotubes selectively placed in an array of short and narrow trenches with a 200 nm pitch in the x direction and 500 nm pitch in the y direction, corresponding to a density of 109 sites cm−2 (scale bar, 400 nm). This demonstrates precise placement in two dimensions (rather than just one dimension with the long trenches in b). As determined from more than 350 trench images, ~90% of the trenches contain at least one nanotube.

  3. Demonstration of high-density carbon nanotube transistors (CNTs).
    Figure 3: Demonstration of high-density carbon nanotube transistors (CNTs).

    a, Optical (left) and SEM (right) images of nanotube transistor arrays with a pitch of 300 nm. Source and drain contacts for the devices in the array are connected by metal leads and pads for electrical testing in a semi-automated probe station. The achievable device density estimated from the device pitch and trench dimension is >1 × 108 transistors cm−2. (Contrast and brightness in the vicinity of nanotubes have been adjusted to make them more visible.) b, Subthreshold characteristics (log(ID)–VG curves) from a subset (310 devices) of total devices on a chip. The yield of electrically connected devices is larger than 90% (evaluated from measurement of 3,312 devices). c, Four representative IDVG data (dots) from the large sets of devices measured in a semi-automated probe station and curves fitted using a parametric function (solid lines). Device parameters (VT, Ion, SS) can be assessed from the fitted curves. Inset: plots in a linear scale. d, Distribution of threshold voltages (left) and inverse SS (right) extracted from measurements of 7,066 semiconducting nanotube transistors on a single chip. The ability to analyse key performance metrics from such a large number of devices provides valuable information regarding variability and yield and is a critical advance for a carbon-nanotube transistor technology.


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  1. IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, USA

    • Hongsik Park,
    • Ali Afzali,
    • Shu-Jen Han,
    • George S. Tulevski,
    • Aaron D. Franklin,
    • Jerry Tersoff,
    • James B. Hannon &
    • Wilfried Haensch


H.P., A.A., G.S.T. and S.H. developed the carbon nanotube placement method. H.P., S.H. and A.D.F. fabricated and characterized the nanotube transistors. J.B.H., J.T. and W.H. developed the model and software for rapid assessment of the large sets of measured data. All authors contributed to discussing the results and writing manuscript.

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