Reduction of thermal conductivity in phononic nanomesh structures

Journal name:
Nature Nanotechnology
Year published:
Published online


Controlling the thermal conductivity of a material independently of its electrical conductivity continues to be a goal for researchers working on thermoelectric materials for use in energy applications1, 2 and in the cooling of integrated circuits3. In principle, the thermal conductivity κ and the electrical conductivity σ may be independently optimized in semiconducting nanostructures because different length scales are associated with phonons (which carry heat) and electric charges (which carry current). Phonons are scattered at surfaces and interfaces, so κ generally decreases as the surface-to-volume ratio increases. In contrast, σ is less sensitive to a decrease in nanostructure size, although at sufficiently small sizes it will degrade through the scattering of charge carriers at interfaces4. Here, we demonstrate an approach to independently controlling κ based on altering the phonon band structure of a semiconductor thin film through the formation of a phononic nanomesh film. These films are patterned with periodic spacings that are comparable to, or shorter than, the phonon mean free path. The nanomesh structure exhibits a substantially lower thermal conductivity than an equivalently prepared array of silicon nanowires, even though this array has a significantly higher surface-to-volume ratio. Bulk-like electrical conductivity is preserved. We suggest that this development is a step towards a coherent mechanism for lowering thermal conductivity.

At a glance


  1. Silicon nanomesh device.
    Figure 1: Silicon nanomesh device.

    a, Silicon nanomesh films are fabricated on SOI wafers by transferring the pattern of two intersecting platinum nanowire arrays (grey) into the silicon epilayer (yellow). The intersecting platinum nanowire arrays are created using the superlattice nanowire pattern transfer (SNAP) technique, which translates the layer spacings within a GaAs/AlxGa(1−x)As superlattice into the width and pitch of a nanowire array30. Two successive SNAP processes are needed to make an intersecting array: the blue layer represents the buried silicon dioxide, and the black layer is the silicon handle layer. b, SEM image of part of a silicon nanomesh film, showing a uniform square-lattice matrix of cylindrical holes. Scale bar, 200 nm. The nanomesh films can have areas of up to 10 × 10 µm2. c, SEM image of a fully released, transparent nanomesh film suspended between two membranes. Scale bar, 2 µm. d, Lower-magnification SEM image showing suspended membranes with platinum heaters/sensors, together with the suspended beams carrying the leads for thermal conductivity measurements. Scale bar, 20 µm.

  2. Device geometries and thermal conductivity measurements.
    Figure 2: Device geometries and thermal conductivity measurements.

    a, Geometry of the two nanomesh films (NM1 and NM2) and three reference systems (TF, EBM and NWA). b,c, SEM images of suspended nanowires in the NWA device (b) and suspended EBM device (c). d, Thermal conductivity versus temperature for two nanomesh devices (diamonds) and the three reference devices. The TF (solid circles) and EBM devices (open circles) have similar thermal conductivities as a result of their similar film thicknesses. The NWA nanowires (open squares) have lower thermal conductivities, a result of their larger surface-to-volume ratios compared to the TF and EBM devices (note the discontinuity in the y-axis). The nanomesh devices, although having significantly lower surface-to-volume ratios compared to the NWA device, exhibit a thermal conductivity that is factor of 2 lower. The error bars on the selected points are representative for the measurements (see Supplementary Information for detailed error analysis). e, To calculate thermal conductivity from the measured thermal conductance, heat is assumed to flow through equivalent, green highlighted channels. The thermal gradient does not have a component perpendicular to these channels. The actual conduction cross-section can only be larger if we account for the interconnecting parts between channels. This approximation gives the upper bound value for the thermal conductivity in nanomeshes.

  3. Electrical conductivity measurements.
    Figure 3: Electrical conductivity measurements.

    Electrical conductivity (measured with a four-point set-up) versus temperature for two nanomesh films (diamonds), both p-type doped with boron to a nominal concentration of 2.0 × 1019  cm−3. Small spatial variations in the doping levels of the silicon epilayers are standard with spin-cast doping, and this is reflected in the different electrical conductivities of the two nominally equally doped devices. Electrical measurements were performed on separate but identically processed devices as those used for thermal conductivity measurements. Both nanomesh devices exhibit values that are comparable to those for bulk silicon thin film (dashed lines; taken from ref. 29). The results imply that the nanomesh films are relatively defect-free and that bulk silicon electrical properties are preserved in the high-doping range.


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Author information

  1. These authors contributed equally to this work

    • Jen-Kan Yu &
    • Slobodan Mitrovic


  1. Division of Chemistry and Chemical Engineering, MC 127-72 1200 East California Boulevard, California Institute of Technology, Pasadena, California 91125, USA

    • Jen-Kan Yu,
    • Slobodan Mitrovic,
    • Douglas Tham,
    • Joseph Varghese &
    • James R. Heath


J.-K.Y., S.M. and J.R.H. conceived the work and wrote the manuscript. J.-K.Y. and S.M. developed the fabrication protocols and carried out fabrication of the devices, transport measurements and data analysis. S.M., J.-K.Y. and J.R.H. interpreted the experimental findings. D.T. and J.-K.Y. devised the experimental set-up, and D.T. wrote the data acquisition, analysis and error propagation routines. J.V. helped with device fabrication. J.V., D.T. and J.-K.Y. wrote the Supplementary Information.

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