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Solution-processed carbon nanotube thin-film complementary static random access memory

Nature Nanotechnology volume 10, pages 944–948 (2015)Cite this article

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Abstract

Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties1,2,3, making them one of the most promising candidates for solution-processable, high-performance integrated circuits4,5. In particular, advances in the enrichment of high-purity semiconducting SWCNTs6,7,8 have enabled recent circuit demonstrations including synchronous digital logic9, flexible electronics10,11,12,13,14 and high-frequency applications15. However, due to the stringent requirements of the transistors used in complementary metal–oxide–semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors16,17,18, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality19,20,21. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

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Figure 1: Complementary SWCNT TFT structures.
Figure 2: Time stability of SWCNT TFT electrical properties.
Figure 3: Large sample statistics of SWCNT TFT electronic properties for |VDS| = 1 V.
Figure 4: SWCNT CMOS SRAM circuit characterization.

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Acknowledgements

This work was supported by the Office of Naval Research MURI Program (N00014-11-1-0690) and the National Science Foundation (DMR-1006391, DMR-1121262 and CCF-0845605). A National Science Foundation Graduate Research Fellowship (M.L.G.) and a NASA Space Technology Research Fellowship (J.J.M.) are also acknowledged. Device fabrication was performed at the NUFAB cleanroom facility at Northwestern University.

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Authors and Affiliations

  1. Department of Materials Science and Engineering, Northwestern University, Evanston, 60208, Illinois, USA

    Michael L. Geier, Julian J. McMorrow, Jian Zhu, Tobin J. Marks & Mark C. Hersam

  2. Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, 55455, Minnesota, USA

    Weichao Xu & Chris H. Kim

  3. Department of Chemistry, Northwestern University, Evanston, 60208, Illinois, USA

    Tobin J. Marks & Mark C. Hersam

Authors
  1. Michael L. Geier
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  4. Jian Zhu
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  6. Tobin J. Marks
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  7. Mark C. Hersam
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Contributions

M.L.G., W.X., C.H.K. and M.C.H. conceived the experiments. M.L.G. fabricated the device, performed the electrical measurements, carried out the atomic force microscopy characterization and analysed and interpreted the data with input from C.H.K., T.J.M. and M.C.H. J.J.M. designed the TFT photolithography mask and wrote the data analysis program. W.X. and C.H.K. modelled the TFTs and SRAM circuits, and designed the photolithography mask for the SRAM circuits. J.Z. sorted the semiconducting SWCNTs and quantified the purity using UV–vis spectroscopy. The manuscript was written with contributions from all authors, and all authors approved the final version of the manuscript.

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Correspondence to Mark C. Hersam.

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The authors declare no competing financial interests.

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Geier, M., McMorrow, J., Xu, W. et al. Solution-processed carbon nanotube thin-film complementary static random access memory. Nature Nanotech 10, 944–948 (2015). https://doi.org/10.1038/nnano.2015.197

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