Solution-processed carbon nanotube thin-film complementary static random access memory

Journal name:
Nature Nanotechnology
Volume:
10,
Pages:
944–948
Year published:
DOI:
doi:10.1038/nnano.2015.197
Received
Accepted
Published online

Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties1, 2, 3, making them one of the most promising candidates for solution-processable, high-performance integrated circuits4, 5. In particular, advances in the enrichment of high-purity semiconducting SWCNTs6, 7, 8 have enabled recent circuit demonstrations including synchronous digital logic9, flexible electronics10, 11, 12, 13, 14 and high-frequency applications15. However, due to the stringent requirements of the transistors used in complementary metal–oxide–semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors16, 17, 18, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality19, 20, 21. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

At a glance

Figures

  1. Complementary SWCNT TFT structures.
    Figure 1: Complementary SWCNT TFT structures.

    a, Optical micrographs of the fabricated SWCNT TFT device with a channel width of 150 μm and length of 50 μm (inset) and an array of SWCNT TFTs. Scale bar, 1 mm. b, Schematic cross-section of a SWCNT TFT fabricated with a SiO2/Si substrate, local Ni (25 nm) gate, Al2O3 (10 nm) gate dielectric, Cr/Au (1 nm/50 nm) source–drain bottom contacts and >99% semiconducting SWCNT thin films. For p-type SWCNT TFTs, the remaining layers are the p-type dopant (∼1.3 μm Shipley S1813 photoresist), an ALD seeding layer (benzyl viologen) and a final encapsulation layer (50 nm Al2O3). For the n-type SWCNT TFTs, the top layers consist of n-type dopant (∼100 nm benzyl viologen) and the final encapsulation layer (50 nm Al2O3). c, Atomic force micrograph of the random network SWCNT morphology in the TFT channel with a linear density of ∼10 SWCNTs per μm.

  2. Time stability of SWCNT TFT electrical properties.
    Figure 2: Time stability of SWCNT TFT electrical properties.

    a, Log-linear transfer (IDSVGS) curves for encapsulated p-type (solid lines) and n-type (dashed lines) SWCNT TFTs measured after initial exposure to atmosphere (blue) and after 7 h of ambient exposure (green) at |VDS| = 1 V. b, Log-linear transfer (IDSVGS) curves for unencapsulated p-type (solid lines) and n-type (dashed lines) SWCNT TFTs measured after initial exposure to atmosphere (blue) and after 5 h of atmospheric exposure (red), with the change in Ioff indicated by the arrow (red/blue). c,d, Log10(Ion/Ioff) of p-type (c) and n-type (d) SWCNT TFTs as a function of ambient exposure time for repeated transfer measurements of a single encapsulated (purple) and unencapsulated (black) SWCNT TFT, where Ion is defined as |IDS| at |VGS| = 2 V and Ioff is defined as |IDS| at VGS = 0 V.

  3. Large sample statistics of SWCNT TFT electronic properties for |VDS| = 1 V.
    Figure 3: Large sample statistics of SWCNT TFT electronic properties for |VDS| = 1 V.

    a,b, Log10(Ion/Ioff) for encapsulated (purple) and unencapsulated (black) p-type and n-type SWCNT TFTs. c, Subthreshold swing for encapsulated (purple) and unencapsulated (black) p-type SWCNT TFTs. d, Log10(IDS) when VGS = 0 V for encapsulated (purple) and unencapsulated (black) n-type TFTs. e, Threshold voltage for encapsulated (purple) and unencapsulated (black) p-type (solid) and n-type (striped) SWCNT TFTs. n, number of devices tested.

  4. SWCNT CMOS SRAM circuit characterization.
    Figure 4: SWCNT CMOS SRAM circuit characterization.

    a, Optical micrograph of a fabricated SWCNT CMOS SRAM cell and corresponding circuit diagram (inset image size, 1 × 0.6 mm) showing the p-type SWCNT TFTs (orange dashed boxes) and n-type SWCNT TFTs (green dashed boxes), as well as an optical micrograph of the large-area array of SWCNT CMOS SRAM cells. Scale bar, 1 mm. b, Read margin measurements (solid lines) and folded read margin measurements using inverted axes (dashed lines) for the initial measurement (purple) and after 40 h (4,000 cycles) of continuous ambient testing (green). c, Hold operation for the wordline (WL) voltage set to VDD, showing no write event (purple), and write operation for the wordline voltage set to 1.25 V for initial (blue) and after 40 h (4,000 cycles) of continuous ambient testing (green) with the intersection  = bitline (BL) (grey). d, Read, write and hold noise margin stability testing for SWCNT CMOS SRAM cells over 40 h (4,000 cycles) of ambient testing. e,f, Histograms of read margin (e) and write margin (f) for hundreds of individual SWCNT CMOS SRAM cells.

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Author information

Affiliations

  1. Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208, USA

    • Michael L. Geier,
    • Julian J. McMorrow,
    • Jian Zhu,
    • Tobin J. Marks &
    • Mark C. Hersam
  2. Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, Minnesota 55455, USA

    • Weichao Xu &
    • Chris H. Kim
  3. Department of Chemistry, Northwestern University, Evanston, Illinois 60208, USA

    • Tobin J. Marks &
    • Mark C. Hersam

Contributions

M.L.G., W.X., C.H.K. and M.C.H. conceived the experiments. M.L.G. fabricated the device, performed the electrical measurements, carried out the atomic force microscopy characterization and analysed and interpreted the data with input from C.H.K., T.J.M. and M.C.H. J.J.M. designed the TFT photolithography mask and wrote the data analysis program. W.X. and C.H.K. modelled the TFTs and SRAM circuits, and designed the photolithography mask for the SRAM circuits. J.Z. sorted the semiconducting SWCNTs and quantified the purity using UV–vis spectroscopy. The manuscript was written with contributions from all authors, and all authors approved the final version of the manuscript.

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The authors declare no competing financial interests.

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