Nature Nanotechnology 1, 42 - 46 (2006)
Published online: 4 October 2006 | doi:10.1038/nnano.2006.53

Subject terms: Electronic properties and devices | NEMS

Giant piezoresistance effect in silicon nanowires

Rongrui He1 & Peidong Yang1

The piezoresistance effect of silicon1 has been widely used in mechanical sensors2, 3, 4, and is now being actively explored in order to improve the performance of silicon transistors5, 6. In fact, strain engineering is now considered to be one of the most promising strategies for developing high-performance sub-10-nm silicon devices7. Interesting electromechanical properties have been observed in carbon nanotubes8, 9. In this paper we report that Si nanowires possess an unusually large piezoresistance effect compared with bulk. For example, the longitudinal piezoresistance coefficient along the left fence111right fence direction increases with decreasing diameter for p-type Si nanowires, reaching as high as −3,550 × 10−11 Pa–1, in comparison with a bulk value of −94 × 10−11 Pa−1. Strain-induced carrier mobility change and surface modifications have been shown to have clear influence on piezoresistance coefficients. This giant piezoresistance effect in Si nanowires may have significant implications in nanowire-based flexible electronics, as well as in nanoelectromechanical systems.

Application of strain to a crystal results in a change in electrical conductivity due to the piezoresistance effect. To evaluate the piezoresistance effect (or electromechanical properties) in nanostructures, mechanical manipulations and electrical measurements must be performed simultaneously. Traditionally, this has been carried out by interfacing the nanostructures with lithographically defined electrodes. Such nanostructure–electrode interfaces8, 10, however, inevitably have stability and reliability issues when subject to mechanical forces. To avoid such interface problems, we have recently developed a chemical vapour deposition process to grow suspended nanowires for piezoresistance testing11.

Silicon nanowires with left fence111right fence or left fence110right fence growth directions were grown in trenches on silicon-on-insulator (SOI) wafers to form bridge structures (Fig. 1; Supplementary Information, Fig. S1). Such bridges are themselves monolithically structured and fully functional devices, enabling direct probing of electromechanical properties. The joints between the nanowires and the trench sidewalls are mechanically robust. As shown in Fig. 1b, the nanowire grew backwards after impinging into the opposite wall, implying a self-welding mechanism. The deflection of these nanowires followed exactly the behaviour of double-clamped beams in our atomic force microscopy experiments12, confirming the rigidity and equivalence of the two joints. The joints also make reliable electrical connections at the nanowire level. Cross-section transmission electron microscopy images show that there is no catalyst metal at either interface (Fig. 1c and e); hence, the wire–wall junctions are simply Si homojunctions with properties determined primarily by carrier distributions. Ohmic behaviour was readily established at the interfaces for the p-type nanowires studied here. The diameters and resistivities of nanowires can be readily controlled. In this study, the nanowires have diameters ranging from 50 to 350 nm and they were made p-type with resistivities of 0.003–10  cm (see Methods).

Figure 1: left fence111right fence-oriented Si nanowire bridges on SOI substrates.

Figure 1 : |[lang]|111|[rang]|-oriented Si nanowire bridges on SOI substrates.

a, Single nanowire with the left fence111right fence growth direction is bridging a trench confined by vertical {111} faces on a left fence110right fence-oriented SOI substrate. The parallel lines on the sidewalls with alternating contrast are scallops formed during deep reactive ion etching. b, General morphology of a bridged nanowire, which grew from the left sidewall along the left fence111right fence direction and impinged upon the opposite sidewall; it finally grew backwards after self-welding into the sidewall. c,e, Cross-sectional transmission electron microscope images for the two joints between the nanowire and trench sidewalls. d, A high-resolution electron microscopy image confirms the left fence111right fence growth direction and reveals a thin oxide layer on the surface of the nanowire. The scale bars in ae are 2 µm, 500 nm, 100 nm, 3 nm and 100 nm, respectively.

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The quantitative relation between conductivity/resistivity and stress/strain is given by the fourth-rank piezoresistance tensor1. When a uniaxial stress is applied and the electric field and current are along the same direction, the longitudinal piezoresistance coefficient13 can be measured and defined as the relative change in conductivity per unit stress:

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where σ0 is the conductivity under zero stress and X is the stress. Traditionally, the piezoresistance coefficient was defined with resistivity1 as πlρ = (Δρ/ρ0)/X. The conversion is simply πlρ = −πlσ for small Δσ. Uniaxial stresses were applied on Si nanowires along their lengths by the four-point bending method14 (Fig. 2a; see Methods); the longitudinal piezoresistance coefficients along the left fence111right fence and left fence110right fence directions, πleft fence111right fenceσ and πleft fence110right fenceσ, were then examined. The measurements on left fence111right fence-oriented nanowires will be focused on in the following discussions.

Figure 2: Longitudinal piezoresistance coefficients πleft fence111right fenceσ of p-type Si nanowires.

Figure 2 : Longitudinal piezoresistance coefficients |[pi]||[lang]|111|[rang]||[sigma]| of p-type Si nanowires.

a, Schematic diagram for the four-point bending setup used to apply uniaxial stresses on Si nanowires. b, The conductance of a p-type left fence111right fence-oriented nanowire (70 nm × 1.2 µm) increases under compressive stresses and decreases under tensile stresses. c, Relationships between the relative change in conductivity Δσ/σ0 and stress/longitudinal strain. Four types of nonlinear behaviours of nanowires are shown, labelled with letters I, C, L and Z. The inset shows the overview for L. d, First-order longitudinal piezoresistance coefficient of p-type Si nanowires and its dependence on diameter and resistivity. Different colours represent different nonlinearities: green, I; black, C; blue, L; red, Z. The drop lines are for use as guidelines. The uncertainties for πleft fence111right fenceσ in the fittings are typically 2.5% for I, 2.7% for C, 13.5% for L and 7.8% for Z categories.

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Figure 2b illustrates typical data taken from the four-point bending measurements, showing that the conductance increases under compression and decreases under tension for a p-type left fence111right fence-oriented nanowire. This trend is qualitatively consistent with the longitudinal piezoresistance behaviour of bulk Si along the left fence111right fence directions. For further quantitative analyses, the relative change in conductance ΔG/G0 was converted to the relative change in conductivity Δσ/σ0 by subtracting the dimensional changes of nanowires (see Supplementary Information). The relationships between Δσ/σ0 and stress X are shown in Fig. 2c. One of the five curves presented is for the boron-doped SOI-device layer, with resistivity 1  cm, as the representative for bulk Si, and the other four curves represent the typical behaviours of Si nanowires. It can be readily seen that the conductivity of a Si nanowire is much more sensitive to stress than that of bulk Si. For instance, under a compression of 8 × 107 Pa, Δσ/σ0 can be as high as 15 for nanowires, but is only 0.08 for bulk Si. Moreover, the piezoresistance effect is generally nonlinear for Si nanowires, but it is essentially linear for bulk Si (refs 1 and 15) in the stress range performed here. The nonlinearities are classified into four categories based on the shape of the (Δσ/σ0)−X curves. A letter is assigned to each category by the similarity in shape between the letter and curve: ‘I’ represents a relatively linear curve, ‘C’ represents a concave curve, ‘L’ is for curves with greater slope under compression, and a ‘Z’ curve is convex with compression and concave with tension. Because of these significant nonlinearities, we fitted Δσ/σ0 as a function of X into the McLaurin series to the third power and took (dσ/dX)/σ0 at zero stress as the first-order piezoresistance coefficient πleft fence111right fenceσ. The second- and third-order coefficients will not be discussed in detail here; however, it is expected that a large second-order coefficient exists in the C and L curves, and a large third-order coefficient in the Z curves.

Further conclusions can be drawn from the statistical data for πleft fence111right fenceσ from nanowires with different diameters and resistivities (Fig. 2d; −πleft fence111right fenceσ was plotted because πleft fence111right fenceσ is negative). Data for bulk Si with different resistivities16 are also shown in the figure (carrier concentrations were converted to resistivities by adopting the empirical relation17). It is clear that πleft fence111right fenceσ for a nanowire (−35 to −3,550 × 10−11 Pa−1) is generally much higher than that for bulk Si (in the range −17 to −94 × 10−11 Pa−1, depending on resistivities16). Only those nanowires with diameters larger than 300 nm and resistivities less than 0.004  cm have values close to that of bulk Si. The resistivity dependence of πleft fence111right fenceσ for nanowires follows a trend similar to that of bulk: the coefficient increases as the resistivity decreases. In addition, the diameter dependence is particularly interesting: the coefficient increases as the diameter decreases. Furthermore, the nonlinearity of the piezoresistance effect also shows a dependence on diameter and resistivity. From the colour-sorted distribution of the four types of nonlinearities, it can be seen that the nanowires with smaller diameters and higher resistivities have L-shaped (Δσ/σ0)−X curves, but those with smaller diameters and lower resistivities possess Z curves. Medium-sized nanowires exhibit C shapes, and I curves are quite typical for larger wires with lower resistivities. It is clear that thinner nanowires generally have greater nonlinearities.

For both theoretical considerations and practical applications, it is worth examining whether carrier concentration or mobility plays the dominant role in these remarkable conductivity changes for nanowires. Strained nanowire field-effect transistors (FETs) were made for such a purpose. Solid polyelectrolyte (LiClO4/poly(ethylene oxide)) was placed over a nanowire to provide surrounding gating18 and transconductances were measured under varied stresses (Fig. 3a; see Methods). The mobility for the device shown here is estimated to be 30 cm2 V−1 s−1 at zero stress and the corresponding carrier concentration is 7 × 1017 cm–3. The relative changes in mobility Δμ/μ0 were compared with the relative changes in conductivity Δσ/σ0 (Fig. 3b). The close match between them indicates that the large piezoresistance coefficient πleft fence111right fenceσ derives mainly from the change in carrier mobility. This mobility origin of the giant piezoresistance effect should have significant implications in strain engineering on the nanometre scale. In the current work, the mobility could be doubled for a nanowire with a diameter of 55 nm under 0.05% compressive strain along the left fence111right fence direction.

Figure 3: Strained Si nanowire field-effect transistors.

Figure 3 : Strained Si nanowire field-effect transistors.

a, Measurements on transconductances under different stresses. The inset shows the schematic diagram for polyelectrolyte gating. b, Comparison between the relative change in mobility Δμ/μ0 and the relative change in conductivity Δσ/σ0. The mobilities are fitted and calculated from VGS = −2.56 V to −2.9 V and the conductivities are taken at VGS = −2.74 V. The nanowire measured here is 120 nm thick and 3.5 µm long.

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The significant enhancement of the piezoresistance effect is not limited to the left fence111right fence direction. Measurements on left fence110right fence-oriented Si nanowires also show very large longitudinal coefficient πleft fence110right fenceσ values. For example, πleft fence110right fenceσ was measured to be −660 × 10−11 Pa−1 for a 75-nm-thick nanowire with resistivity 0.3  cm (the bulk value for p-type Si is πleft fence110right fence,bulkσ = −70 × 10−11 Pa−1 for the same resistivity16). Strained FET experiments also showed the mobility origin for the change in conductance (see Supplementary Information for detailed discussions).

For p-type bulk Si, πleft fence111right fence  π44 and πleft fence110right fence  π44/2, where π44 is the shear coefficient. π44 originates from the change in mobility through carrier transfers and effective mass changes when the band structures of Si are modified by strains19. The mobility origin for πleft fence111right fenceσ and πleft fence110right fenceσ in Si nanowires suggests that the enhanced piezoresistance effect will be based on modifications on the band structures. The reduced dimensions and increased surface-to-volume ratio should further contribute to the enhancement.

We note that the slightly enhanced piezoresistance effect has been previously reported in Si beams defined by electron-beam lithography20. Some systematic studies on inversion layers of Si metal-oxide-semiconductor devices21, 22, 23 have also been carried out. Several anomalous effects, such as sign reversing from bulk to inversion layers (p-type) for π11 and π12, were observed and attributed to the quantization of carriers in the inversion layers. In the case of the nanowires reported here, the quantum confinement simply due to size reduction does not seem evident, given that the diameters of the nanowires are larger than 50 nm. However, the surface effect may contribute significantly here24. This surface effect was tested by a series of surface modifications on the suspended nanowires. The as-grown nanowires generally have ~1-nm-thick oxide layers on their surfaces (Fig. 1d). We used HF solution to make the surfaces hydrogen-terminated and used HNO3 solution to recreate the oxide layers. The conductance of a nanowire was observed to decrease after the treatment with HF or during the immersion in buffered HF; it was brought back by the oxidation in HNO3 (Fig. 4). The piezoresistance coefficient, however, showed the opposite trend compared with the conductance; that is, it increased after HF treatments and decreased after HNO3 treatments. These results indicate the importance of surface states in the enhanced piezoresistance effect. Generally, a built-in potential can be readily created near Si surfaces due to Fermi-level pinning at the surface states25, 26, which would mediate the carrier concentrations and induce quantization in the space charge layers27. Different surface states have different energy levels and density of states, which would result in different built-in potentials. So, different carrier concentrations and quantization in the space charge layers are expected for different types of surface states. This influence of carrier concentrations on the piezoresistance coefficients has been experimentally demonstrated in the trend shown in Fig. 2d. The possible effect of quantization needs to be simulated in further theoretical work.

Figure 4: Effects of surface states on the piezoresistance coefficient.

Figure 4 : Effects of surface states on the piezoresistance coefficient.

The piezoresistance coefficient varies with surface states but remains large. It shows an opposite trend with respect to the conductance during surface treatments. The dotted lines are used as guidelines. a and b correspond to two different nanowires. The diameters of the nanowires are about 90 nm.

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We have shown that p-type Si nanowires exhibit unusually large longitudinal piezoresistance coefficients. Systematic theoretical calculations are required to reveal the underlying mechanisms for the observations. The enhanced piezoresistance effect could find applications in Si nanotechnology, flexible electronics28, as well as in nanoelectromechanical systems. In particular, intrinsic strains may exist in many nanoscale materials29, and strain sensitivity could be a basic issue affecting the performance of these nanostructure-based electronics.



Synthesis of Si-Nanowire Bridge Structures

Si nanowires were grown by using SiCl4 as the precursor in the CVD process. Nanowires with left fence111right fence growth directions were synthesized at 850 °C by using Au particles as the catalyst, and nanowires with left fence110right fence growth directions were grown at 900 °C by using Pt films as the catalyst. For bridge structures, taking the left fence111right fence nanowires as the example, trenches with {111}-face sidewalls were fabricated on left fence110right fence-oriented SOI wafers. The left fence111right fence nanowires would grow perpendicularly to the sidewalls and impinge onto the opposite sidewalls to form suspended bridges (Fig. 1a). In a similar way, left fence110right fence-nanowire bridges were formed on left fence111right fence-oriented SOI wafers. The device layer is 5 µm-thick and the buried oxide is 2 µm-thick for all the SOI wafers. Nanowires were doped with boron by using BBr3 as the source. Single-nanowire-bridged trenches, such as the one shown in Fig. 1a, could be produced at a relatively high yield for single-nanowire-based measurements.

Electrical Measurements

Thin Al wires were directly bonded onto Si pads by ultrasonic power to complete the connections for electric measurements. The contacts are ohmic and have resistances of ~100  . The SOI device layer was doped with boron with a resistivity of 0.01  cm, and the Si pads coupled with trenches have resistances of ~50 . These two resistances are only 0.001 to 0.1% of the resistance of a Si nanowire and can be neglected in the measurements. Four terminal electrical measurements were applied for SOI device layers.

Four-Point Bending Method

The SOI substrate with Si-nanowire bridges, together with a control bare SOI substrate side-by-side, was adhered firmly onto a 1.2-mm-thick steel plate using epoxy. Both substrates were aligned to have their device left fence111right fence/left fence110right fence directions parallel to the longitudinal direction of the steel plate. When the plate was subject to four-point bending (Fig. 2a), uniaxial stresses were created longitudinally in the pure bending region (between the two inner supports)30. Any transverse stresses (estimated to be 10% of the longitudinal stresses), which could be generated in the Si substrates due to the difference in Poisson's ratio between the steel and Si, will not be transferred to the Si nanowires, because the nanowires are suspended with only the two ends mechanically anchored to the Si substrate20. The non-uniformity of stresses was found to be only ~0.01% across the nanowire's diameter, which was determined by the ratio of the diameter to the distance from it to the plate's neutral axis. So, nanowires are believed to be subjected to uniaxial stresses to a very accurate degree in four-point bending experiments. Tensile stresses were generated on the nanowires in the bending direction shown in Fig. 2a, and compressive stresses were obtained by reversing the bending direction. It was ensured that the compressive stresses applied were less than the critical stresses to prevent the nanowires from buckling (see Supplementary Information). A foil strain gauge was glued on the surface of the control substrate to measure the longitudinal strains, which were converted to stresses by multiplying by Young's modulus (Young's modulus for nanowires is similar to that of bulk12). The strains measured by the foil gauge were checked to ensure consistency with the deflections of the plate. Measurements on SOI-device layers gave approximate values (with about +5% error) of πleft fence111right fenceσ due to the existence of transverse stresses; they were used as the bulk references to check the consistency of the experiments. πleft fence111right fenceσ measured from device layers was close to the value of bulk Si; for example, πleft fence111right fenceσ  −80 × 10−11 Pa−1 for a device layer with resistivity of 1  cm. πleft fence111right fenceσ was also checked for the device layer (0.01  cm) on every sample, with consistent values of −57 ± 5 × 10−11 Pa−1.

Polyelectrolyte Gating

An extra Al wire was bonded on the SOI oxide surface near the nanowire as the gating electrode. LiClO4 and poly(ethylene oxide) were mixed by weight ratio 0.15:1 in methanol and briefly heated at 80 °C to form a gel-like polyelectrolyte. The polyelectrolyte was placed over the nanowire and the Al wire to provide surrounding gating via the electric double layer established at the nanowire–polyelectrolyte interface. The mobilities were calculated from the slopes of the linear region in the transfer characteristics, in which the capacitance from the native oxide layer on the nanowire was considered. The polyelectrolyte was considerably soft and expected to have negligible influence on the mechanical behaviour of the nanowires.

Chemical Modifications of Si Nanowire Surfaces

5% HF solution or 10:1 (NH4F/HF) buffered HF solution (for immersion) was used to provide hydrogen termination and 70% HNO3 was used to oxidize the surfaces. All the treatments took 30 s except for the immersion experiments.



We thank A. San Paulo and Rong Fan for technical assistance, and R. Maboudian and R. T. Howe for helpful discussions. This work was supported by the U.S. National Science Foundation and MARCO MSD Center. We thank the National Center for Electron Microscopy, Lawrence Berkeley National Laboratory, Berkeley, for the use of their facilities.

Competing interests statement

The authors declare no competing financial interests.

Received 23 June 2006; Accepted 30 August 2006; Published online 4 October 2006.



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  1. Department of Chemistry, University of California, Materials Science Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720, USA

Correspondence to: Peidong Yang1 e-mail: p_yang@berkeley.edu


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