FIGURE 1. Dual processor.

Nishiguchi and colleagues' pattern-recognition processor⁴ uses two basic components that each consist of two capacitatively coupled transistors: a transfer transistor (T-FET) and a detector transistor (D-FET). The probability that an electron will tunnel from the source of the T-FET, under the gate and into the storage node is determined by the source voltage, which is set by the value of a bit i in the input image, and by the gate voltage, which is set by a bit r in the reference image. The more electrons accumulate in the T-FET storage node, the lower the current that flows through the capacitatively coupled D-FET. In the instance depicted, both the input and reference bits are turned on, i = r = 1, and electrons accumulate in the storage node, reducing the detector current. The second unit (right) is fed with the inverse inputs of the first, and . If the original inputs were matched at 0, the inputs here would be 1, and this half of the processor would record the depleted current characteristic of matched bits. (Figure adapted from ref. 1.)