Supplementary information

Supplementary Information

The first section 'Magnetologic gates for high speed electronics' contains the discussion of the ways in which the signal-to-noise can be improved, and it discusses the different capacitive parasitic effects present in the system. The second section 'Thyristor latch' contains a description of the thyristor latch which we use to convert the transient current into a voltage. The third section 'Power budgeting' contains the calculation of the power dissipated by a system of ~106 magnetologic gates. The fourth section 'Magnetization errant dynamics: data retention, write fault and half selection' qualitatively explains how the possible sources of errors in magnetic random access memories (due to magnetization switching) are eliminated in our spin-logic design. The fifth section contains Supplementary Methods with a detailed account of the time-dependent lateral diffusion equations which we have used in our calculations (figure 2 of the main text).

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