1. Department of Physics, University of California San Diego, La Jolla, California 92093-0319, USA

Correspondence to: H. Dery¹ Correspondence and requests for materials should be addressed to H.D. (Email: hdery@ucsd.edu).

Abstract

Research in semiconductor spintronics aims to extend the scope of conventional electronics by using the spin degree of freedom of an electron in addition to its charge¹. Significant scientific advances in this area have been reported, such as the development of diluted ferromagnetic semiconductors^{2, 3}, spin injection into semiconductors from ferromagnetic metals^{4, 5, 6, 7, 8} and discoveries of new physical phenomena involving electron spin^{9, 10}. Yet no viable means of developing spintronics in semiconductors has been presented. Here we report a theoretical design that is a conceptual step forward—spin accumulation is used as the basis of a semiconductor computer circuit. Although the giant magnetoresistance effect in metals^{11, 12} has already been commercially exploited, it does not extend to semiconductor/ferromagnet systems, because the effect is too weak for logic operations. We overcome this obstacle by using spin accumulation rather than spin flow^{13, 14, 15}. The basic element in our design is a logic gate that consists of a semiconductor structure with multiple magnetic contacts; this serves to perform fast and reprogrammable logic operations in a noisy, room-temperature environment. We then introduce a method to interconnect a large number of these gates to form a 'spin computer'. As the shrinking of conventional complementary metal-oxide–semiconductor (CMOS) transistors reaches its intrinsic limit, greater computational capability will mean an increase in both circuit area and power dissipation. Our spin-based approach may provide wide margins for further scaling and also greater computational capability per gate.

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