FIGURE 3. Proposed logic cascading scheme.

The output from a magnetologic gate, L_a, propagates into two similar gates, L_b and L_c. Lines with arrows denote current-carrying wires. Other lines hold binary voltage signals, which help to synchronize the flow of information and also steer the high level current I_h between the pass gates labelled by p1, p2 and p3. The synchronization process is managed in three phases by the thyristor latch (see text and Supplementary Information). In the first phase, the binary voltage signals are low except for clk1 at two inputs (dotted lines). This signal synchronizes two operations: one to prepare the thyristor latch to receive a signal and one to switch the pass gates p1 to their low resistance mode, thus directing the high current I_h to flow primarily in the upper horizontal black wire. During the second phase, clk2 is high and I_h flows primarily in the wire over the top of the middle contact of L_a. The locally induced magnetic field rotates the magnetization of this contact and thus triggers the transient current labelled by 'in'. The thyristor latch is synchronized by clk2 to capture this response. In the third phase, clk3 is high and one of the voltage signals V_A or V_B at the output of the thyristor latch is also high. Whether V_A or V_B is high depends on the amplitude of the transient current. This directs I_h into one of two opposite paths (respectively, blue or red wires), resulting in magnetic encoding of '0' or '1' in the relevant operands (A, B, X or Y) of L_b and L_c. Although not shown, during the three-phased action each magnetologic gate sends its output and then receives the four inputs for the next three-phase cycle.